1 00:00:01,920 --> 00:00:08,700 How does the sequential circuit use a memory cell in a typical FPGA in this lecture, taking the general 2 00:00:08,700 --> 00:00:10,270 sequential circuit definition? 3 00:00:10,560 --> 00:00:12,090 I'm going to handle this question. 4 00:00:15,550 --> 00:00:18,410 The term sequential means one after another. 5 00:00:18,910 --> 00:00:24,770 Therefore, we expect that operations and tasks are executed one after another in order. 6 00:00:25,570 --> 00:00:30,310 So there should be a mechanism to keep track of the status of the sequence. 7 00:00:30,700 --> 00:00:34,770 Memory elements are an excellent candidate to save the states. 8 00:00:35,320 --> 00:00:41,980 A typical structure of a sequential circuit has two main parts a combination or circuit that performs 9 00:00:41,980 --> 00:00:49,090 the logic of the tasks and the memory part that stores the state execution sequences and transfers data 10 00:00:49,090 --> 00:00:50,500 between these sequences. 11 00:00:51,480 --> 00:00:56,250 As memories in FPGA commonly used flipflops as the building blocks. 12 00:00:57,310 --> 00:01:03,790 A clock signal should determine the time boundary between two sequences of executions and triggers, 13 00:01:03,790 --> 00:01:07,650 saving the states and data generated by the combination of certain. 14 00:01:08,970 --> 00:01:15,210 The combination of circuit in each sequence should use the input data, as well as the data in the memories 15 00:01:15,510 --> 00:01:19,080 to generate outputs and then you memory contents. 16 00:01:20,400 --> 00:01:25,330 The previous diagram is general enough to represent all sequential circuits. 17 00:01:26,320 --> 00:01:30,070 However, this diagram shows more details here. 18 00:01:30,330 --> 00:01:37,230 I have emphasized that the memory part can get some data directly from the design primary inputs and 19 00:01:37,230 --> 00:01:41,070 give some data directly to the design primary outputs. 20 00:01:43,400 --> 00:01:45,100 Let's consider this simple sequel. 21 00:01:46,290 --> 00:01:53,220 Which consists of a single fall, it accepts an end with binary value and generates it's even part of 22 00:01:53,220 --> 00:01:53,460 it. 23 00:01:55,260 --> 00:02:00,270 Default is not unrolled, so it's sequential RTL Circuit should implement the. 24 00:02:01,670 --> 00:02:08,210 This article circuit consists of an X or gate to perform the functionality added flip flop to save the 25 00:02:08,210 --> 00:02:11,510 temporary data, which here is the part it. 26 00:02:12,640 --> 00:02:18,260 Note that the hotel circuit also has some circuits to keep track of Loop Iterations index. 27 00:02:19,000 --> 00:02:23,200 However, for the sake of simplicity, I have ignored that part. 28 00:02:26,060 --> 00:02:27,980 Let's consider one iteration of the loop. 29 00:02:29,350 --> 00:02:34,120 It consists of one logic operation, which is an exercise and a simple assignment. 30 00:02:34,810 --> 00:02:41,290 However, if you look at the operation carefully, it consists of three tasks Rippey from the Flipflop 31 00:02:42,100 --> 00:02:44,770 perform XOL functionality right back. 32 00:02:44,770 --> 00:02:45,970 The result to the different. 33 00:02:51,540 --> 00:02:59,070 Note that in this example, the value is provided by the function input, and we assume that it is available 34 00:02:59,190 --> 00:03:00,720 throughout the whole task. 35 00:03:01,620 --> 00:03:03,750 And we don't need to read that from memory. 36 00:03:04,860 --> 00:03:11,850 A set of wires can implement a variable, please recall the combination also could implementation concepts 37 00:03:12,420 --> 00:03:14,550 presented in the previous course. 38 00:03:17,780 --> 00:03:22,430 And this is like I'm going to demonstrate the sequence of execution of this, Luke. 39 00:03:23,750 --> 00:03:30,110 Later, we use this concept to design a sequential circuit in Etchells, therefore understanding this 40 00:03:30,110 --> 00:03:32,030 simple sequence is essential. 41 00:03:32,840 --> 00:03:36,320 Let's assume that only one clock cycle is required to perform. 42 00:03:36,320 --> 00:03:43,000 The logic operation of the body represented by the Aldgate T denotes the clock period. 43 00:03:45,250 --> 00:03:51,190 Then in the first class period, the design designer initialized party bit saved in a flip flop and 44 00:03:51,190 --> 00:03:57,280 generate the new parity bit and write that into the same degree for the same functionality is performed 45 00:03:57,280 --> 00:03:59,500 in the second cycle and afterwards. 46 00:04:05,700 --> 00:04:08,940 Let's review the same sequence for a general sequential search. 47 00:04:10,060 --> 00:04:15,190 As I mentioned before, this figure models the general sequential circuit, it consists of two main 48 00:04:15,190 --> 00:04:18,490 parts, a combination of circuit and memory cells. 49 00:04:19,580 --> 00:04:24,980 The circuit also receives inputs and the clock signal and generates outputs. 50 00:04:31,210 --> 00:04:37,090 Again, we assume that the combination of circuit performs its task in one clock cycle. 51 00:04:38,330 --> 00:04:45,530 Then this diagram shows the circuit execution sequence in each clock cycle, the combination of circuit 52 00:04:45,770 --> 00:04:52,050 reads the data and state performs its task and write the new state into the memo. 53 00:04:52,120 --> 00:04:59,210 Results will back to this concept later in the next section to get some idea for designing a group of 54 00:04:59,210 --> 00:05:01,070 sequential circuits in Etchells. 55 00:05:05,810 --> 00:05:12,560 The clock signal is essential in sequential seconds as it orchestrates all Dealogic activities in the 56 00:05:12,560 --> 00:05:18,050 design, but what are the signal characteristics in the next lecture? 57 00:05:18,200 --> 00:05:19,520 I will answer this question. 58 00:05:21,630 --> 00:05:27,100 These are the takeaway messages from this lecture, the sequential circuit consists of a combination 59 00:05:27,100 --> 00:05:29,070 of circuit and a set of memories. 60 00:05:29,700 --> 00:05:32,880 Memory cells can store the circuit states or data. 61 00:05:36,190 --> 00:05:43,450 Now, the quiz question, consider this simple C-code show the execution sequences of the code using 62 00:05:43,450 --> 00:05:45,720 the corresponding simplified hardware structure.