1 00:00:00,330 --> 00:00:05,820 What is the basic memory, so in a typical FPGA in this lecture, I'm going to introduce you to the 2 00:00:05,820 --> 00:00:12,000 smallest memory cell in the FPGA, which is the underlying component of all other types of memories 3 00:00:12,000 --> 00:00:13,010 inside an FPGA. 4 00:00:15,460 --> 00:00:21,100 As we learned in the previous course, combination of circuits are composed of basic logic gates and 5 00:00:21,100 --> 00:00:24,460 perform the functional tasks without any memory storage. 6 00:00:25,480 --> 00:00:32,340 However, some circuits and designs should save data or states temporarily or permanently. 7 00:00:32,770 --> 00:00:36,340 These types of circuits are called sequential circuits. 8 00:00:39,990 --> 00:00:47,130 The basic memory cell using in almost all Fijis is flipflop, which can save a single bit logic value, 9 00:00:47,820 --> 00:00:53,750 a simplified model of a flip flop, accepts to input signals and generates an output signal. 10 00:00:54,510 --> 00:00:57,180 The input signals are data and clock. 11 00:00:57,510 --> 00:00:59,970 The output signal is the flipflopped state. 12 00:01:02,960 --> 00:01:09,260 The data signal carries the next the state of the flipflop, but it cannot be saved in the memory until 13 00:01:09,260 --> 00:01:15,080 the clock signal gives permission, this permission usually happens at the age of the clock. 14 00:01:16,420 --> 00:01:22,810 Either off rising or falling EDG can give permission, and it depends on the type of the given flipflop 15 00:01:23,560 --> 00:01:29,250 flipflop that receives the data input signal and activates at the edge of the clock is called the flop. 16 00:01:29,770 --> 00:01:36,100 If you assume the rising edge, then at each rising edge, the value of D is saved in the flipflop as 17 00:01:36,100 --> 00:01:38,920 its current state and is shown on the output signal. 18 00:01:41,190 --> 00:01:44,220 In this timing diagram, we have two rising ages. 19 00:01:44,430 --> 00:01:49,920 The first one put the value of zero and the second one put the value of one into the FILIPO. 20 00:01:51,020 --> 00:01:54,410 A table can demonstrate the functionality of a deeply flawed. 21 00:01:55,410 --> 00:02:00,630 As shown in this table, the rising age of the clock saves the data into memory. 22 00:02:03,060 --> 00:02:09,750 To clarify the flip flop behavior, let's take an example, assume to flip flops that are connected 23 00:02:09,750 --> 00:02:10,570 sequentially. 24 00:02:11,280 --> 00:02:13,260 These are the clock and data signals. 25 00:02:13,800 --> 00:02:16,320 We are going to find it to output signals. 26 00:02:16,320 --> 00:02:23,340 Q1 and Q2, the rising age of the clock, runs the input data to the different floor and the first rising 27 00:02:23,340 --> 00:02:26,030 edge and Q1 are zero. 28 00:02:26,520 --> 00:02:30,090 Then the Q1 and Q2 should both be zero. 29 00:02:32,070 --> 00:02:40,320 At the second rising edge, the D and Q one are one and zero respectively, then the Q1 and Q2 should 30 00:02:40,320 --> 00:02:41,790 be one and zero. 31 00:02:43,400 --> 00:02:50,780 And the third rising edge that the and Q one are zero and one respectively, then the Q1 and Q2 would 32 00:02:50,780 --> 00:02:59,260 be zero and one finally at the last rising edge of the clock, the D and Q1 are one and zero respectively. 33 00:02:59,540 --> 00:03:02,900 Then the Q1 and Q2 would be one and zero. 34 00:03:06,870 --> 00:03:12,590 Now that we know how the deeply flawed works, the question would be how does a sequential circuit use 35 00:03:12,600 --> 00:03:14,790 a memory cell in a typical FPGA? 36 00:03:15,570 --> 00:03:17,570 The next lecture will answer this question. 37 00:03:20,760 --> 00:03:26,730 These are the takeaway messages from this election, do flipflop is the basic memory cell inside an 38 00:03:26,730 --> 00:03:30,030 effigy that can save one bit of data. 39 00:03:31,790 --> 00:03:37,330 The flip flop requires the rising or falling age of the clock signal to save input data. 40 00:03:39,500 --> 00:03:47,120 Now, the question, consider this design and the data signal, find a Q1 and Q2 signals or the time.