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How can we describe the stop, a motor driver that implements the two phase one method, this lecture

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will guide you through the steps to design such a circuit in why decisions?

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As I mentioned earlier in the section, to drive a sleeper motor with two phase unmetered, we should

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repeatedly apply this waveform to the state of the waveform has four steps.

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Each step the to calls for a state FSM can model this behavior.

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Let's ascribe to the state machine invited us.

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But before that, let's have a big picture of the final design.

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The design consists of two ipis, the first Sipes, the Supermoto driver.

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That implements the FSM, as mentioned earlier, and the second i.p generates regular pulses that are

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used for triggering state transitions in deficit.

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Creating a White House such as project with the name of a Stepa on this underscore driver Dash White

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Essentialists choose the supper on this Kamata underscore driver as a design top function name.

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Don't forget to select the basis to report as a target FPGA platform.

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Download the design enforcement files and add them to the project.

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Open the design, Sourcefire.

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As a design has for states and enumeration data type defines.

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Then the design to function with two arguments is defined, the first argument is an input signal that

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determines the motorcoach signal.

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The second argument is a form without that provides the motor driving signals, then we need a static

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variable.

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To hold a design state, this variable will be synthesized into a register in the final HAGA.

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Two temporary variables saved intermediate values for the state variable and the design only out.

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Now we need the state machine to implement the waveform of the two phase on method explained earlier

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in this lecture, each state first checks the input motor clock.

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If it is one, then it goes to the next state.

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Otherwise it stays in the current state.

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In addition, in each state to output, bits are active.

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Finally, we should update the state register and send out the output value.

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Now synthesize the code and generate the corresponding afterlife.

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For performing the logic syntheses, create a new view of the project with the name of Stepa underscore

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to underscore driver Deshwal and choose the basis three borders target FPGA platform.

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Create a new blank design and add to eyepiece to define the repository.

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A Supermoto clock pulse and a supermodel right then and the ipis into the designer, you can connect

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them together, make their remaining port excel and modify the external port names properly.

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Download the design consent pie from the resources folder attached to this selection and add that to

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the project's now general activities, Three-Month Program Board.

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How can we control the number of rotating steps in the next lecture?

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We'll answer this question.

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These are now takeaway messages, and FSN with four states can implement the two phase one method,

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the two phase one method energises two codes of the state's initial step.

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Now, the quiz question, how can you find a stable angle in a motor specific?