What is a linear feedback shift register, Eleazar?
And how can we use that for a pseudo random number generator?
This lecture will address these questions, in addition, it will explain how to describe that dimensionless.
A linear feedback shift register at FSR is a shift register whose input it is a linear function of its
previous state.
The most commonly used linear function of single bits is an exclusive or.
Therefore, I FSR is usually a sheep producer whose input bit is the X or of some of its value.
It's one of the main applications of the elephants are is generating pseudo random numbers and modulo
two polynomial can be used to represent an Alpha SA, which is called its characteristic polynomial.
The coefficients of this polynomial are ones or zeros.
The one coefficients correspond to the connections to the first bit.
For example, in this example, positions zero, one, two, three and four denoted by X zero x1 x2
three and four respectively have connections to the first.
This is another FSR example, along with its characteristic polynomial.
Let's consider this three with an officer.
The initial value of their FSR is called the sea, the sea, it cannot be zero.
Because the operation of the register is deterministic, this stream of values produced by the register
is completely determined by its current or previous state.
Likewise, because the register has a finite number of possible estates, it must eventually enter a
repeating cycle.
However, another officer with a well chosen feedback function can produce a sequence of bits that appears
random and has a very long cycle and end with FSR that has two to the power of and minus one.
Different states called maximal length.
It positions that affect the next estate are called the tax.
In this diagram, the tops are 16, 14, 13 and 11.
A maximum length of FSR produces an end sequence.
The thing is, it cycles through all possible due to the power of and minus one two states except for
the state where all bets are Zeitels.
The following table lists maximum length polynomials for analysis.
Now, we should describe another FACA in place for this purpose, let's consider this 32 bit maximum
length Alcazar.
Please pay attention to the bit indices, which is a slightly different from the area indices in C,
C plus plus the C function describing the FSR accepts a 32 bit and a single bit inputs as the C and
the load sigma.
We should define a static variable as a shift register.
Please consider the bits indices in this variable.
If the little signal is one we initialize, the letters are with the C, this diagram shows the officer
with the modified indices.
Now, let's describe the feedback function.
And finally returns that FSR value.
Now, let's ascribe that FSR based digital dice in white Essentialists.
First of all, open the White House and create a new project with the name of Dyce, underscore, roller,
underscore LFR Dash White secessionists to the dice, underscore roller, underscore LFR as a design
top function name and selected basis to report and the target FPGA class for.
Download the design and test bench files from the resources folder attached to the selection and the
files to the creative project.
How we look at the design Sourcefire, the pseudo random stop function implements that officer explained
earlier in this lecture.
They get suspension calls that FSR and returns modulars six plus one of the random.
If it is the first time it passes the seat with one on the loud signal to the al FSR functio.
They're designed to function checks, the roll input, if it is one, then it calls the Getaround function,
then returns a certain segment code corresponding to the received a random number.
Notice that the pipeline optimization pragma is applied to the top function.
The test bench function is very similar to the test bench function explained in the previous lecture.
Now, let's simulate the code and synthesize that.
The analysis perspective confirms the risky design approach as a design initiation in turmoil is what?
Now let's explore the IP and instantiate that in a we want to project.
Created, we want a project with the name of Dyce, underscore, roller, underscore FSR Dashboard and
select the basis storyboard as the target FPGA class for.
Create a new blog design and the generated IP, along with the bouncer and a pulse generator, ipis
into the Riverdale, the repository.
And ipis to the design area and connect them together, change the port names appropriately.
Download the consent file from the resources folder attached to this lecture and add that to the wider
project.
Now, generally, down products create the ideal wrapper and finally generate the FPGA with three programmed
FPGA and examine the design on the board.
And this video is the last letter in the section that explains how to implement a digital device on
the basis report, the next lecture will give you a few exercises to practice and master what you've
learned throughout this section.
These are our takeaway messages.
And officers can be used to generate pseudo random numbers.
And with maximum length and officer has to go to the power of and minus one state's.
Now, the police question right there, telescope for analysis are with this feedback polynomial.