1 00:00:01,030 --> 00:00:07,090 How can we design the counter based digital dice for the basis through what this lecture will cope with 2 00:00:07,090 --> 00:00:07,660 this question? 3 00:00:09,790 --> 00:00:15,970 Our digital life circuit receives a one bit input, which is connected to a push button and generates 4 00:00:15,970 --> 00:00:21,070 a random number between one and six that will be shown on a seven segment display. 5 00:00:21,550 --> 00:00:27,300 The counter based approach utilizes a 32 bit counter to model a spinning wheel. 6 00:00:28,410 --> 00:00:35,370 The counter continuously counts between zero to two to the power of 32 minus one, then whenever we 7 00:00:35,370 --> 00:00:39,440 push the button, we'll read the counter while it is still running. 8 00:00:40,410 --> 00:00:46,290 Then we can find the modulus six of the number, which results in a number between zero and five. 9 00:00:46,800 --> 00:00:51,780 Incrementing this number generates the final random number between one and six. 10 00:00:54,770 --> 00:01:01,070 Now, let's implement our idea in this open the way to such a list and generate a new project with the 11 00:01:01,070 --> 00:01:05,460 name of dice, underscore, roller, underscore, counter dash. 12 00:01:05,480 --> 00:01:06,170 What is a. 13 00:01:07,630 --> 00:01:14,620 Accordingly, choose unrest, caroler underscore counter as a design to function and select the basis 14 00:01:14,620 --> 00:01:17,050 three as the underlying FPGA board. 15 00:01:37,490 --> 00:01:43,430 Download the design and test files from the resources folder attached to this lecture and add them to 16 00:01:43,430 --> 00:01:44,060 the project. 17 00:01:56,410 --> 00:02:02,770 The design, Heather Fine, defines an array containing the seven segment codes, four digits from zero 18 00:02:02,770 --> 00:02:03,190 to nine. 19 00:02:04,260 --> 00:02:11,340 The Getaround function and the design Sourcefire implement a circular 32 bit counter that should continuously 20 00:02:11,340 --> 00:02:12,990 count in each clock cycle. 21 00:02:14,770 --> 00:02:22,060 It returns the Modula six plus one of its current number, when we call that the top function, has 22 00:02:22,060 --> 00:02:29,650 an input argument called Rove connected to a push button and two outputs that will drive a seven segment 23 00:02:29,650 --> 00:02:31,360 display on the basis three board. 24 00:02:32,540 --> 00:02:39,320 The pipeline optimization is also applied on the top, one of the top function defines a static variable 25 00:02:39,320 --> 00:02:42,110 that contains the last generated random number. 26 00:02:43,100 --> 00:02:46,100 It calls the Getaround sub function in each Cluck's cycle. 27 00:02:47,120 --> 00:02:53,360 Note that we expect that the description follows the risky design approach, which means its initiation 28 00:02:53,360 --> 00:02:57,440 into a wall is one and the top function is called in each clock cycle. 29 00:02:58,040 --> 00:03:04,040 The top function checks the roll input and if it is one, it selects the number generated by the function 30 00:03:04,220 --> 00:03:05,720 as the final random number. 31 00:03:06,650 --> 00:03:10,390 Note that the rolling input is connected to a push button on the board. 32 00:03:14,150 --> 00:03:19,610 The last two lines in the top function send the corresponding seven segment code and enabled signals. 33 00:03:26,830 --> 00:03:33,730 That has been Sourcefire defines a map variable to return the BCT number corresponding to each segment 34 00:03:33,730 --> 00:03:41,380 code, then the main function calls are designed to function several times in Tunis looks the inner 35 00:03:41,380 --> 00:03:47,300 loop uses a random number of iterations to call the top function while the roll signal is zero. 36 00:03:48,130 --> 00:03:54,130 This loop model, the time when the design runs in the PJ and push button is not pressed. 37 00:03:55,110 --> 00:04:01,770 The outlook calls the top function with the roll signal equal to one, in this case, the design generates 38 00:04:01,770 --> 00:04:02,570 a random number. 39 00:04:03,270 --> 00:04:06,180 Let's simulate the code and check it out. 40 00:04:18,010 --> 00:04:24,760 Now, let's synthesize the code and make sure that the result of the design is pipelined with the initiation 41 00:04:24,760 --> 00:04:25,750 interval of one. 42 00:04:36,810 --> 00:04:40,380 The analysis perspective confirms this expectation. 43 00:04:41,750 --> 00:04:45,320 As can be seen, the initiation interval is one clock cycle. 44 00:04:46,300 --> 00:04:49,570 Whereas the design latency is thirty seven cycles. 45 00:04:52,620 --> 00:04:56,850 Now let's explore the Arctic IP to be used in every one of the projects. 46 00:05:09,180 --> 00:05:14,280 Creative, you want the project with the name of dice, underscore, roller, underscore, count or 47 00:05:14,280 --> 00:05:18,660 dashboard and select the basis to report as a target FPGA platform. 48 00:05:36,850 --> 00:05:43,900 Create a new blog design and the generated IP, along with the bouncer and pulse generator IPS into 49 00:05:43,900 --> 00:05:45,370 the pivotal repository. 50 00:06:18,440 --> 00:06:23,780 And I appeal to the design area and connect them together, changed a port named appropriately. 51 00:07:59,820 --> 00:08:05,790 Download the consent file from the resources folder attached to this lecture and add that to the report 52 00:08:05,810 --> 00:08:06,510 of the project's. 53 00:08:56,570 --> 00:09:03,590 Now, generate down to product, create the ideal wrapper, and finally generate FPGA bitstream, program 54 00:09:03,590 --> 00:09:06,120 the FPGA and examine the design on the board. 55 00:10:29,710 --> 00:10:36,520 What is the pseudo random number generator and how can we use that to implement the digitalise the next 56 00:10:36,520 --> 00:10:38,730 lecture will answer these questions. 57 00:10:42,990 --> 00:10:47,780 This is our takeaway message acounter can be used to implement is spinning. 58 00:10:50,660 --> 00:10:57,440 Now, the question changed the code to implement a circular counter from one to six and check the design 59 00:10:57,440 --> 00:10:58,190 on the FPGA.