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How can we use the interface to detect the key press in a four by four keyboard?

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This lecture will address this question.

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For the keyboard module, I'm using the digital and pimlott keypad, which is a 16 button keypad, the

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keyboard utilizes for rows and columns to create an area of 16 push buttons while driving the column

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lines with a low level logic voltage one at a time.

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We can read the corresponding logic level voltage on each of the rows to determine which button, if

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any, is currently being pressed.

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Therefore, our Pyrmont key parts controller will have four states on each state, one column is derived

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with logic value zero.

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Then Rose will be right.

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The key at the intersection of the column and the row with zero value is written as the key.

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We should perform this scanning methodology regularly with the frequency of about sixty two point five

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kilohertz, which means with the period of 16 millisecond.

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Our design consists of two ipis, the first type detects the pressed key and show that on a single cell

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and segment display, this IP has three outputs.

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One drives the key with columns and to drive a certain segment to display the key.

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It also has five inputs, a design clock, a reset, a refresh clock signal, and the status of keyboard

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rose.

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The second IP generates the pulses with four millisecond per.

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Used for the transition between states.

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Now, let's describe our design in each of us here.

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I will explain the first IP which detects depressed key for the second IP we can use the IP that generates

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click refresh pulses described in seven segments section create a new Y to such as project with the

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name of Pimlott underscore keyboard dash white essentialists choose the design top function name.

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Don't forget to select faces three born as a target FPGA platform.

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Artisan conference attached to this lecture and the resources to the creator project upon the design

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of their fight, we see it to the constant Arry after including the AP header file.

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This area contains the binary index of each key on our keypad, then a constant area represents all

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the southern segment codes for the hex numbers from zero to.

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Openly designed Sourcefire.

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As therefore, as of our design has four states, we define an enumeration type to represent these states.

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They're designed to function, has five arguments, two inputs and outputs.

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Following the key design approach, the function is parked right now, we need to register to save the

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second state.

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We also need to register to keep the active column in each state.

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Then we define two variables corresponding to these two resistors, these variables keep the intermediate

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values temporarily.

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We also define two other variables that we need throughout the code.

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Now let's have a look at the states in the first set, cold, cold one.

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If the input refresh signal is one, then the time slot of this state has been expired and we should

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go to the next state called call to.

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And the second column should be driven by zero if they state call one time slot is not expired, it

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should apply the logic value zero to the first column and read the rules and check which one is zero.

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If he has been pressed, the state should return the index of that key.

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If no keys pressed, then the no key pressed variables should be activated.

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Other states do a similar task.

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Finally, we should update the state registers and prepare now.

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Now let's synthesize the code and generate the corresponding vivants to.

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Create a new one on the project, choose Pimlott underscore keyboard that should be Varnedoe as a project

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name, and don't forget to choose bases to be bought as a target FPGA platform.

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Create a new blog designed.

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At the generated IP and the signal pulse generator to deliver on the IP repository.

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Added to Ipis into the design area.

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Connect them together and modify the name of external ports, if you like.

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Create a new constraint, fine, and the required constraints.

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We need a set of constraints to define the clock port.

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Also, we should connect the seven segment data and enable signals.

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The arrest report can be connected to the center pushbutton.

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Finally, we should provide the connections between the design and JCP must signal signal-to-noise.

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Now generate the.

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I have forgotten to change the clock and reset things, so let's modify them and generate the bitstream

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again.

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Now we can program the board and examine the design.

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This lecture is the last in this section that explained how to work with modern interface in the next

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lecture concludes a section by posing a few exercises for you to master the concepts.

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This is our takeaway message to detect oppressed key on a four by four mattocks keyboard, we can apply

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a low level logic voltage on the column lines once at a time.

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And read the corresponding logical level voltage on each of the rows.

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Now, the question, modifying the keyboard controller code to make that a single cycle design.