1 00:00:01,010 --> 00:00:08,150 How can we control a simple lady using the Pimlott interface available on the basis to report this lecture, 2 00:00:08,390 --> 00:00:09,530 will answer this question. 3 00:00:12,010 --> 00:00:17,920 We are going to control and LLC, which is outside the bases, three bought via Pimlott interface. 4 00:00:20,590 --> 00:00:28,660 The basis the report contains three payment interfaces denoted by J, JBI and Jayce, this figure shows 5 00:00:28,660 --> 00:00:35,470 the PMA pin configuration on the basis to reward a payment on the sport has 12 pins arranged in two 6 00:00:35,470 --> 00:00:35,950 rows. 7 00:00:37,780 --> 00:00:43,760 Interface provides to power to ground an eight signal pince. 8 00:00:45,650 --> 00:00:53,000 All the signal pins are connected to the FPGA pins such that the design inside FPGA can communicate 9 00:00:53,000 --> 00:00:58,870 with Piemonte interfaces with Connect the Ground of the Circuit to the Jayce five pin. 10 00:00:59,660 --> 00:01:05,120 Also, we connect the register connected to the Leidy today see one on the Pyrmont interface. 11 00:01:05,660 --> 00:01:11,660 We also connect the FPGA design, input and output ports to its light switch on the board and the ping 12 00:01:11,660 --> 00:01:13,750 connected to JSI one respectively. 13 00:01:17,420 --> 00:01:23,410 Create a new White House socialist project with the name of Pimlott Underscore Leidy, the Bush White 14 00:01:23,420 --> 00:01:28,150 House Etchells Choose Pimlott underscore Alyda as a design top function. 15 00:01:28,820 --> 00:01:34,670 Don't forget to choose the basis to report as the underlying FPGA platform ensured that the Viviendo, 16 00:01:34,670 --> 00:01:38,900 the IP flow target option, is selected under the floor target feature. 17 00:01:41,060 --> 00:01:45,260 Create a new design file with the name of Pimlott, underscore the. 18 00:01:46,880 --> 00:01:50,570 Make sure that the final location is inside the created project. 19 00:01:52,600 --> 00:01:58,210 Created, designed to function with two boolean arguments, one as input and the other as output. 20 00:02:00,600 --> 00:02:07,500 Then, after defining the port interfaces assigned to input argument to doubt, now synthesize the design 21 00:02:07,620 --> 00:02:09,930 and generate the corresponding Valdai. 22 00:02:29,720 --> 00:02:35,270 Creating you, we run the project with the name of Pimlott, Underscore Alyda, that you choose the 23 00:02:35,270 --> 00:02:37,670 basis to be born as a target FPGA platform. 24 00:03:00,840 --> 00:03:06,090 Cowritten new blog design and idea generated Pimlott the IP to the IP repository. 25 00:03:31,920 --> 00:03:37,650 And the IP to the design area and make their port external change the port names as shown. 26 00:03:56,780 --> 00:04:03,110 Then create a consent form, we need to consent to connect the input design port to a slight switch 27 00:04:03,110 --> 00:04:05,810 and the output port to the PC one. 28 00:05:00,480 --> 00:05:02,340 Creativity stream and programmable. 29 00:05:57,540 --> 00:06:00,630 Now you can turn on and off the lid using this light switch. 30 00:06:08,040 --> 00:06:13,620 How can we read the keyboard connected to a remote interface, the next lecture will cope with this 31 00:06:13,620 --> 00:06:14,010 question. 32 00:06:16,210 --> 00:06:22,870 These are our takeaway messages that promote interface provides the power and ground signals for a connected 33 00:06:22,870 --> 00:06:28,280 peripheral eight signal of mode interface is connected to the FPGA pins. 34 00:06:29,890 --> 00:06:36,220 Now, the police question connect 16 of what LSD to the basis three bought and then control them with 35 00:06:36,220 --> 00:06:39,340 16 as light switches are available on the basis triple.