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How can we design an uptown four digit counter with lower than initial value in this lecture will design

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such a.

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Ardizzone counter has four outputs representing four digits.

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It counts from zero to nine thousand nine hundred and ninety nine.

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It has two inputs to determine the Counting Direxion account, and it also accept an integer value between

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zero to nine thousand nine hundred and ninety nine to initialize the count.

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To perform the initialization, we need a one bit input signal called load the counter counts in both

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directions.

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In this lecture, we described this four digit counter in Atlas, however, to make it operational.

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We need a few other IPIS to be integrated into every Wilander project.

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We need a certain segment driver that was designed in previous lectures.

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We will uSwitch, the bouncer and pulse generator IPIS to connect the up, count down count and load

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inputs to push buttons on the basis through both.

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When you press the push button, the pulse generator, it generates a single cycle pulse to drive the

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corresponding counter input.

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Let's design the counter inviter such as?

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Create a new white essentialist project with the name of four unrestored digit underscore countered

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that she wanted such.

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Then create new design and test bench files, as usual.

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Open the design, Heather Fine, and include the AP underscore in that.

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Openly design source for it, include the design header for it, then define the design top function

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with eight arguments for inputs and four hours as only 14 bits represent a number between zero to nine

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thousand nine hundred and ninety nine, the counter value variable has fourteen bits.

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And the port interfaces also make the design pipeline we need to register to save the counter value.

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Also, we need a temporary variable corresponding to the defined register.

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Now we can check the load signal, if it is one, we can initialize the counter, then we check the

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account signal and if it's one Winkelmann the count to come down here, we should check that down on

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the score.

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Countering after performing the count main tasks, we should extract the four decimal digits.

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Finally, we should modify the counter register, please note that as a design is simple, we don't

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need to implement any stage.

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Now, open the test bench for include design Heather Fine and another design top function prototype

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opened the test by Sourcefire, include the test bench Heather and I assume Feis right.

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The main function and defined is not swayable.

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Define a set of variables, represent the design arguments.

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Now call the design with zeroes onload uptown and downtown signals.

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We can generate a set of single cycle pulses on the upcoming put in a nested look while calling the

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design.

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Now let's perform the simulation.

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The output confirms the correctness of their description.

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Let's perform the high level syntheses.

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Often the analysis perspective noticed that the design is pipelined with the initiation interval of

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one, although it's latency is about 17 cycles.

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As initiation in turmoil is one, the design can accept inputs on every clock cycle.

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After performing the RTL Sea Coast simulation, we can analyze the design waveforms in Rebadow waveform

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formatted.

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As can be seen, a single cycle on the up count, input increments, the count.

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Now we can export the IP to be used in every one of the projects.

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Corradini will be one of the project with the name of four underscored Daejeon, underscore counter

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that SHIRADO choose the Basis three report as a target FPGA platform.

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Create a new blog design.

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At five trips to devote vital repository, as shown here, you can find for IPIS in the resources folder

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attached to this lecture.

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The four digit counter IP into the design area.

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Then at the certain segment, Roger Ipis and connect them to the counter IP.

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Then the bouncer and pulse generator office and connect them to load up, count and down counting place,

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you can change the external port names if you wish.

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Now, download the Constantine file attached to this lecture and add that to the blogger project.

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Now, synthesizer designed and programmed aboard.

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As this video is the last lecture in the section that explains the designing techniques to work with

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seven segments, the next lecture will give you a few exercises to practice and master what you've learned

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throughout this section.

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This is our takeaway message applying the pipeline optimization to a circuit can improve its performance,

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even if it's latencies hard.

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Now, the police question, what would happen if we remove the pragma natural gas pipeline from the

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Cote?