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After understanding the idea behind the sermon segment driver Succot, let's ride the corresponding

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Etchells in this lecture.

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As I mentioned before, our CNN segment Driver Circuit consists of two behind IPIS generated by wired

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to suchness, signal generator and the driver to display the seven segment numbers.

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We start with designing the signal generator and then we design the display driver.

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We should refresh the southern segment by concentrate here.

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I assume that the refresh rate is 16 millisecond, then we should generate a sequence of single cycle

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pulses with a constant period, which is a quarter of the refrigerator.

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Therefore, the signal period is four milliseconds.

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If we assume that the design clock period is ten nanoseconds, then 400000 cycles fit in a single period.

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As you may notice, this signal generator circuit was one of the utility circuits that we designed earlier

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in this course, you can find the corresponding source files of this IP in the resources folder attached

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to this lecture.

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Let's quickly review the IP code invited us wise to such a project with the name of someone underscore

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segment underscore signal Dasch why the Socialists and choose the bases to be born as a target FPGA

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platform.

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Download the design and Test match files from the resources folder attached to this lecture and add

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them to the created project.

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Have a look at the design here for the macro signal, Andras Calpurnia is defined as the number of clock

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cycles fit in a single period.

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There are two definitions.

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One for the final article IP, which is 400000 and the other for the simulation purposes, which is

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10.

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The design source, Fine, contains a simple state machine implemented with an if else statement.

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And it has been a source file called the design top function several times in fall.

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Let's choose the value often for the signal underscore carrier to perform the simulation.

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The simulation output shows that the circuit generates a sequence of regular passes for the desired

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period.

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Now let's perform the sentences and then RTL CECO simulation and have a look at the signal waveforms.

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Signal waveforms also confirm the cycle accuracy of our design.

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Now for generating the article IP, we should change the signal undisclosed period Macross to 400000.

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Now the design should be synthesized again after finishing the high level syntheses export the corresponding.

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The display driver circuit receives for visitor numbers and generates the corresponding segment data

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and control signals as it is a sequential circuit.

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It receives a design clock signal and a result.

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If former state a state machine model the driver behavior.

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Each state provides data for one and segment, we also need a reference signal to trigger the transition

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between states.

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Let's write a driver code, each of us.

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Curity new white essentialist project with the name of seven underscore segment underscore driver dashboard

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to service to the seven underscore segment underscore driver as a top function name.

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Don't forget to choose the basis to report as a target of PJ.

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Download the design and test files from the resources folder attached to this lecture, add them to

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the creative project.

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Let's review the cuts first opened the design Heather, it includes AP underscore Intertek hydrofoil.

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It also defines a constant area containing the seven segment codes corresponding to the digits from

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zero to nine.

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Now open the design source file after including the header file, an enumeration type defines the state's.

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The design to function contains seven arguments, five inputs and outputs, the function is pipelined

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aswell.

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We also need to design port interfaces.

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A static labor holds the design state according to our design coding style, we define temporary variables

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corresponding to outputs and the circuit state.

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Now we need a forest state, state machine.

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We can use a switch statement to implement that initial state, the circuit sends out the data and control

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signals for one seven segment.

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The state transitions occur when the state machine receives a high voltage level on the reference signal

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as a reference signal provides a single cycle positive pulse.

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The state transitions happen regularly.

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In the end, we modified the state's register and Outsports.

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The test bench had a fight includes the design halophiles and the design top function prototype.

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Firstly, the test bench source file defines a match between seven segment codes and the digits from

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zero to nine.

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This map helps us to generate a more readable output after simulation.

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The main function body defines the required variable, then it calls the design several times.

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To generate regular passes for the design reference signal to nested loops are used, whereas the reference

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signal is zero throughout the inner loop execution, it becomes one in the outer fold.

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So using this technique, we generate a regular pulse with the period of 10 cycles that can be examined

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during the simulation.

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Now let's simulate the code and checked out.

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In the printed output, you see the number shown on a certain segment along with the corresponding seven

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segment control signals.

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Also, we can see that after every 10 repetitions, the circuit goes to the next state because of receiving

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a positive pulse on the input reference signal.

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Now, let's synthesize the code and check the reports.

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If you go to the analysis perspective, we can see that each function execution requires two clock cycles

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to finish.

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However, the function is pipelined with the initiation into one on one so it can accept input data

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on each clock cycle.

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Now we can perform the artillery simulation and check the signal waveforms.

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As we can see, when the circuit receives a positive level on the reference signal, it goes to the

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next state and drives the corresponding southern segment.

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Now clears the way for we are an export party, like ready for integrating the design ships and if you

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want to project.

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Now that we have generated the required lips for our Sun segment Drybar, we should connect them together

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any we want to project and generate the FPGA with a stream and check the design on the basis rebought.

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The next lecture will do this task.

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This is our takeaway message using this loops in the test range, we can generate different types of

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periodic input signals for the design on their test, which is described using the technique.

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Now, the question, why are there two clock cycles between the rising edge of the refresh signal and

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data changes on the seven segment signals?