1 00:00:01,890 --> 00:00:07,800 In this lecture, we are going to take an example to demonstrate the performance metrics of a pipeline 2 00:00:07,800 --> 00:00:08,280 designed. 3 00:00:12,300 --> 00:00:20,040 IIR filters are the most efficient type of filters to implement in digital signal processing and are 4 00:00:20,040 --> 00:00:27,090 filter receives a sequence of data as its inputs and generates another sequence of data as its output. 5 00:00:28,240 --> 00:00:32,770 This equation shows the relation between elements in these two sequences. 6 00:00:35,490 --> 00:00:42,420 Here is the feed forward, filter order by are the feed forward filter coefficients. 7 00:00:45,530 --> 00:00:47,720 Q Is the feedback filter older? 8 00:00:48,700 --> 00:00:51,490 I are the feedback filter questions. 9 00:00:53,080 --> 00:00:58,710 This diagram shows the graph that is used to represent an air filter in the literature. 10 00:01:01,720 --> 00:01:09,430 Let's assume P and Q are two, then this would be the IRR equation, this equation can be described 11 00:01:09,430 --> 00:01:10,070 in us. 12 00:01:10,480 --> 00:01:14,830 First, we should define the top function with an input and output parameters. 13 00:01:15,370 --> 00:01:20,950 Then we need for static variables to save two samples of input and output data. 14 00:01:22,960 --> 00:01:28,360 The Exxon and and variables represent the current input and output data. 15 00:01:29,290 --> 00:01:37,090 Now we can write our arithmetic expression, then we should modify the state variables and finally returned 16 00:01:37,090 --> 00:01:37,720 output. 17 00:01:39,610 --> 00:01:43,600 Let's synthesize this code, invited specialists and explore the design. 18 00:01:47,520 --> 00:01:54,240 Create a new white to such a project with the name of IRR, that's why the Socialists choose the IRA 19 00:01:54,360 --> 00:01:58,710 as a top function name and select the basis three as the underlying FPGA board. 20 00:02:09,660 --> 00:02:16,200 And the design and test testament to the created project, you can find the files in the resources folder 21 00:02:16,200 --> 00:02:17,160 attached to this lecture. 22 00:02:32,100 --> 00:02:38,970 Let's have a look at what defines the design header file includes the AP underscoring that point and 23 00:02:38,970 --> 00:02:42,780 defines the data type and the five IRR coefficients. 24 00:02:43,800 --> 00:02:48,540 The design file includes the IRR top function explained earlier in the selection. 25 00:02:57,770 --> 00:03:02,880 The test one charter flight includes the design header file and defines the top function prototype. 26 00:03:03,970 --> 00:03:06,370 It also defines the empowerment. 27 00:03:07,620 --> 00:03:13,720 The test bench main function calls, they are designed eight times and pronounced output on the screen. 28 00:03:14,280 --> 00:03:17,070 It also compares the results with the Golden Model. 29 00:03:32,520 --> 00:03:38,640 Now we can run the simulation, the output confirms the correctness of the design functionality. 30 00:03:53,330 --> 00:03:59,900 Let's remove the pipeline pragma and synthesize the code as a design is multi cycle circuit, we should 31 00:03:59,900 --> 00:04:06,950 change the design block interface from AP, underscore, citral, underscore none to underscore Setara 32 00:04:07,100 --> 00:04:11,730 underscore X to be able to run the R TLC code simulation. 33 00:04:12,440 --> 00:04:19,910 This interface adds some extra signals to the RTL module, such as Sarte Ideal, and that helps the 34 00:04:19,910 --> 00:04:25,010 RTL simulation to detect the start and end of each function iteration. 35 00:04:27,930 --> 00:04:33,810 This interface, along with a couple of other interfaces, will be explained in a separate section. 36 00:04:44,600 --> 00:04:51,980 The synthesis report shows that the design initiation interval is three cycles and the latency is two 37 00:04:51,980 --> 00:04:52,640 cycles. 38 00:04:52,920 --> 00:04:59,600 Now let's perform the archaeological simulation and show the waveforms in the revised away from the. 39 00:05:04,200 --> 00:05:10,650 As can be seen, the circuit can accept a new input every three clock cycles and generate the corresponding 40 00:05:10,650 --> 00:05:12,690 output after two clock cycles. 41 00:05:16,380 --> 00:05:21,270 Therefore, the initiation interval is three and the latency of the design is to. 42 00:06:23,850 --> 00:06:28,560 Now, let's apply the pipeline optimization to the design and synthesize the code. 43 00:06:35,710 --> 00:06:43,150 As a nation in turmoil of the pipeline design is one, we can change the module interface to AP, TRL 44 00:06:43,420 --> 00:06:46,340 none or the APC, TRL. 45 00:06:47,350 --> 00:06:49,420 Now let's perform the high level syntheses. 46 00:07:38,350 --> 00:07:45,190 The synthesis report determines that the design innovation turbo is one and it's latency as is still. 47 00:07:46,180 --> 00:07:50,380 Now we can perform the archaeological simulation and check the waveforms. 48 00:07:58,740 --> 00:08:04,220 As can be seen, the design can accept input and generate output in every clock cycle. 49 00:08:41,000 --> 00:08:47,150 As this video is the last lecture in this section that explains the idea and design techniques, the 50 00:08:47,150 --> 00:08:51,920 next lecture will give you a couple of exercises to practice the proposed techniques. 51 00:08:56,710 --> 00:08:58,420 These are our takeaway messages. 52 00:08:59,360 --> 00:09:06,230 The pipeline optimization improves the design throughput, we cannot perform the archaeological simulation 53 00:09:06,620 --> 00:09:11,180 in multi cycle design with Apsey TRL non module interface. 54 00:09:15,170 --> 00:09:21,020 Now, the quiz question, what is the throughput of the Iowa design without pipeline optimization?