1
00:00:01,810 --> 00:00:08,470
How can we use the function pipelining in using the multi cyclicity counter mentioned in the previous

2
00:00:08,470 --> 00:00:13,860
lecture, this section will explain how to synthesize that into pipelined micro architecture.

3
00:00:16,530 --> 00:00:19,230
This is the last coat of our BCT count.

4
00:00:20,290 --> 00:00:26,280
To guide the sentences to to synthesize the code into a pipeline micro architecture, we only need to

5
00:00:26,280 --> 00:00:31,720
find the pragma in the function body and sentences, too, will take the responsibility of the rest.

6
00:00:32,860 --> 00:00:35,760
Let's see the results in Nevada, Etchells tools.

7
00:00:39,000 --> 00:00:45,870
Create a project with the name of BCT, underscore, counter, underscore pipelining that we do this

8
00:00:46,320 --> 00:00:52,350
and that the design and test bench parties, you can find the files in the resources folder attached

9
00:00:52,350 --> 00:00:52,970
to this lecture.

10
00:00:53,760 --> 00:00:55,350
Let's examine the files.

11
00:00:56,370 --> 00:01:00,600
The design header file has an array containing the seven segment codes.

12
00:01:02,240 --> 00:01:05,450
The design source, fine, contains the BCT counter.

13
00:01:18,730 --> 00:01:26,290
The test bench file contains, of all the calls are designed to function 12 times as we cannot see the

14
00:01:26,290 --> 00:01:29,120
impact of the pipelining in the simulation.

15
00:01:29,470 --> 00:01:32,230
I haven't printed the design outputs on the screen.

16
00:01:32,380 --> 00:01:39,430
Now let's go to the design function and apply the pipeline optimization program in the directive to

17
00:01:39,670 --> 00:01:40,030
right.

18
00:01:40,030 --> 00:01:42,850
Click on the top function and select insert directly.

19
00:01:43,510 --> 00:01:49,690
Then in the white essentialist directive EDITA select the pipeline directive and select the source file

20
00:01:49,810 --> 00:01:50,770
as a destination.

21
00:01:53,180 --> 00:01:59,000
The default value for the initiation interval is one, so you don't need to write anything for this

22
00:01:59,000 --> 00:02:05,230
option after clicking on the OK button, you should see the pipeline pragma under the top function.

23
00:02:09,840 --> 00:02:14,880
Now, let's save the find and perform the simulation and the high level syntheses.

24
00:02:24,760 --> 00:02:30,480
And the report's summary, you can see that the initiation into all of the design top function is one.

25
00:02:30,910 --> 00:02:32,920
Let's go to the analysis perspective.

26
00:02:33,430 --> 00:02:37,660
As can be seen, each function call requires two clock cycles to finish.

27
00:02:39,830 --> 00:02:46,460
However, the design is pipelined with the initiation interval of one, which means it can accept input

28
00:02:46,460 --> 00:02:47,510
in each class cycle.

29
00:02:48,140 --> 00:02:53,210
Now we can perform the RTL CECO simulation and open the way for the viewer.

30
00:03:13,500 --> 00:03:18,270
The way forms confirm the design accepts its input in each click cycle.

31
00:03:34,280 --> 00:03:38,300
Now we can close the window and explore the corresponding article IP.

32
00:03:42,890 --> 00:03:46,640
Created behind the project and instantiate the exported IP.

33
00:03:47,660 --> 00:03:53,450
Then connect the pulse input to a push button switch through the balancer and pulse generator epis.

34
00:03:55,420 --> 00:04:02,230
Then at the constant fight, you can find the IPPs and the constant fight in the resources folder attached

35
00:04:02,230 --> 00:04:02,830
to this lecture.

36
00:04:06,430 --> 00:04:08,840
Generate FPGA bitstream and programmed about.

37
00:04:26,670 --> 00:04:30,930
Now test the design on the wall in contrast to our previous implementation.

38
00:04:31,220 --> 00:04:34,680
You will notice that the design responses to each click on the push-Button.

39
00:04:53,640 --> 00:04:59,340
To better understand the pipeline design behavior, the next lecture will introduce a few performance

40
00:04:59,340 --> 00:05:01,290
metrics for an art hill design.

41
00:05:06,610 --> 00:05:12,490
These are our takeaway messages, I think pipeline pragma to a function can improve its performance

42
00:05:12,670 --> 00:05:14,620
and the rate of accepting input data.

43
00:05:16,140 --> 00:05:21,090
See, simulation cannot show the impact of the pipeline optimization on a function.

44
00:05:26,070 --> 00:05:32,040
Now, the quiz question, what would happen if we change the design top function pipeline pragma as

45
00:05:32,040 --> 00:05:32,610
follows?