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What is the harder pipelining technique?

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How can it be described in a sequential circuit?

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This lecture will define the pipelining, concepts and their usage in designing sequential circuits.

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Pipelining is a micro architectural technique to execute tasks at the same time, with some timing overlaps,

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let's consider a few tasks that should be executed sequentially to process a stream of data.

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These tasks can encapsulate in a function or a loop statement.

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Each task needs the results of its predecessor to generate its outputs.

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Therefore, they cannot perform in a full parallel fashion.

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Examples of this scenario are the assembly lines in a factory.

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One way to execute these tasks is the sequential execution in which the system receives new data when

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it completely processed the previous one.

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In this case, each input data should wait sometimes to be processed.

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Another execution mechanism is pipelining in which TASC executions can overlap.

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Let's have a look at this execution model first task one receives the first data and gives its results

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to task to then while tasked to process the massive data task, one can accept the second data.

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In the next iteration, one task, three process the first data, the second task can process the second

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data and task, one can receive the third date.

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In this scenario, the input data are processed without any delay.

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The tasks in the pipeline, micro architecture also referred to as stages.

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Pipelining allows the stages to be executed concurrently, each stage does not have to complete all

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its operations before it begins, the next stage pipelining is applied to functions and loops.

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Let's recall the single cycle sequential circuit design techniques.

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In which the combination, all part requires one clock cycle to complete its task, in this scenario,

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the design can receive the input data at each clock cycle.

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Now, what would happen if the conventional circuit requires more than one clock cycles to finish?

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Let's assume it needs to clock cycles.

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This diagram shows the timing execution.

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As can be seen, the second cannot accept inputs at all clock cycles.

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It only accepts input every other clock cycle.

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Therefore, the second may miss some inputs or inputs should wait to be processed.

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Let's consider the previous sequential circuit that its combination or circuit requires to clock cycles

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to do its task.

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If it is, why the combination or circuit into two stages or two subtasks with some registers in between,

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then we can employ the pipeline execution.

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In this case, why the second estate, that is to performs its task, the first stage that is Taiwan

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accepts new data.

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Therefore, the circuit can receive data at each clock cycle.

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The number of clock cycles between two input data in a pipeline micro architecture is called the initiation

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interval and for an efficient pipeline, it should be one.

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In this case, the initiation interval is one.

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How can you describe function pipelining in the next lecture will describe this concept.

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These are our takeaway messages, pipeline execution increases the task throughput by exiting and generating

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more data than sequential execution.

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What?

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The initiation interval is the number of clock cycles before the function can accept new input data.

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The ideal initiation interval is one.

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Now, the quiz question assume that the combination of part of the sequential circuit takes three clock

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cycles to finish are the timing diagram of its pipeline implementation with initiation interval of one.