1
00:00:02,280 --> 00:00:08,480
The single cycle design approach in Etchells is not always applicable to designing logic circuits,

2
00:00:08,940 --> 00:00:15,260
therefore, some circuits described in Etchells will be synthesized into a multi cycle design article

3
00:00:15,270 --> 00:00:15,840
description.

4
00:00:16,590 --> 00:00:20,610
Now the question is how can we optimize a multi cycle RFL circuit?

5
00:00:21,720 --> 00:00:27,060
This section will answer this question by introducing hardware pipeline optimization.

6
00:00:34,650 --> 00:00:41,190
This section's main goal is to introduce the function pipelining concept in Etchells to optimize a multi

7
00:00:41,190 --> 00:00:44,250
cycle hardware description to achieve this goal.

8
00:00:44,820 --> 00:00:50,970
This section will define the function pipelining and Etchells and a few performance metrics to evaluate

9
00:00:50,970 --> 00:00:51,660
designs.

10
00:00:57,430 --> 00:01:03,340
These are the objectives of this section, understanding the function pipelining in Etchells, applying

11
00:01:03,340 --> 00:01:08,470
the function pipelining to motorcycle designs, evaluating the pipeline design.

12
00:01:12,020 --> 00:01:19,310
This section consists of seven lectures, this video as the first lecture clarifies the goal of this

13
00:01:19,310 --> 00:01:20,930
section and it's a structure.

14
00:01:22,220 --> 00:01:26,870
The next lecture will define and introduce the concept of function pipelining and Etchells.

15
00:01:28,700 --> 00:01:33,170
They should be the motorcycle designer, Nicholas will be explained in lecture three.

16
00:01:35,000 --> 00:01:38,650
And three approaches are proposed to cope with this issue.

17
00:01:40,720 --> 00:01:45,960
How to use the function pipelining invite to such a list is explained in the fourth lecture.

18
00:01:47,110 --> 00:01:54,100
Lecture five will introduce a few performance metrics to evaluate pipelined Etchells Description's Lecture

19
00:01:54,100 --> 00:02:00,850
six will put all the concepts together to propose an efficient implementation for an infinite impulse

20
00:02:00,850 --> 00:02:02,760
response IRR filter.

21
00:02:03,400 --> 00:02:09,640
The last lecture, as usual, gives you a couple of exercises to master the techniques explained throughout

22
00:02:09,640 --> 00:02:10,240
the section.

23
00:02:18,150 --> 00:02:24,260
After finishing this section, you will be able to utilize function pipelining, optimization initialised,

24
00:02:24,960 --> 00:02:30,030
evaluate a pipeline description initialised and compare that with other implementations.

25
00:02:35,210 --> 00:02:39,050
The next lecture will explain the concept of function pipelining fleshless.

26
00:02:43,390 --> 00:02:45,160
These are our takeaway messages.

27
00:02:46,180 --> 00:02:53,590
Dealing with motorcycle designs is essential function pipelining is a technique to provide a high performance

28
00:02:53,590 --> 00:02:54,670
motorcycle design.

29
00:02:57,290 --> 00:03:03,590
Now the question, what is the difference between single cycle and multi cycle design implementations?
