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As the HLS design flow is a new topic, its learning requires a step-by-step approach with several examples. 
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The structure of this course is based on this assumption.
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This course is the second step towards using HLS to design logic circuits and accelerators for FPGA-based platforms, which its focus 
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is on sequential circuits.
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In this course, I will take the HLS approach to explain the fundamental concepts in designing sequential 
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circuits. I assume that you are familiar with the HLS-based approach to design combinational 
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circuits explained in the first course of this series. 
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This course looks at FPGA from a high-level perspective without going into the low-level hardware details.
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This course would give you the foundation of using HLS for digital design in Xilinx-based FPGAs 
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to enhance your productivity compared to the traditional HDL design flow. 
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The only prerequisite for this course is the “High-Level Synthesis for FPGA, part 1-combinational circuit” 
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course, and you don’t need to read any specific document.
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However, referring to Xilinx documents, especially “Vitis High-Level Synthesis User Guide-UG1399” 
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-UG1399” is recommended. For more examples and discussions about the HLS-based design approaches,
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you can refer to the highlevel-synthesis.com web-log-site or the course Github site. 
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If you have any questions or issues regarding the concepts and codes presented in this course, please 
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refer to the Q&A section.
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In this course, you’ll learn How to use HLS design flow to implement sequential circuits and how to 
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work with state-of-the-art HLS software tools to implement arithmetic, logic and control circuits on 
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hardware.
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This is a practical course. Throughout the course, 
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I will explain the concepts of FPGA structure, software tools, HLS techniques, and coding styles 
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to implement several examples.
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This course comprises four parts. The first part is called prologue, which introduces the course
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and its structure throughout two lectures. 
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The current video is the second lecture.
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The second part is called “setup”, 
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which gives a big picture of the HLS for FPGA and its design flow and how to install related software 
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tools and set up the target FPGA board. 
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It consists of one section, including five lectures, from lecture 3 to 7. The third part explains 
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how to develop sequential circuits using C/C++ language in HLS. 
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This part consists of 11 sections and 77 lectures.
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Finally, the last part puts all explained techniques together to implement three exciting projects. 
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It consists of three sections and 18 lectures.
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The course parts are designed to cover all classical concepts and techniques in sequential logic design 
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for FPGA implementation.
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The first project implements a Digital Dice circuit. The corresponding section 
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will explain two different techniques to generate a random number in hardware.
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The second project implements UART modules to exchange data serially between the Basys3 board 
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and a computer. 
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The last project designs a logic controller to control the rotation of a stepper motor. 
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Each lecture describes a single idea which is presented through a couple of slides. The first slide 
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tells the topic and the motivation, 
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then it follows by a few slides explaining the main ideas and concepts. 
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After that, a slide gives the motivation of the next lecture by posing a question. 
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This slide also creates a conceptual link between two consecutive lectures. 
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Then I summarise the lecture contributions through a few takeaway messages.
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The last slide in each lecture contains a quiz that helps you to concentrate on the main idea.
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In this course, I have considered the Xilinx Basys 3 FPGA board as our target platform. Basys 3 is an 
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entry-level development platform based on the latest Artix-7 Xilinx FPGA designed exclusively for 
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Vivado Design Suite.
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This board is cheap and accessible by almost all students, researchers and individuals. 
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However, the concepts and techniques explained in this course are valid for all other Xilinx FPGAs.
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What is the structure of the LAB environment that will be used throughout this course? The next lecture 
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will answer this question.
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The takeaway messages are.
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This course explains the fundamentals of sequential digital designs using the Xilinx HLS toolset
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You don’t need to have in-depth hardware knowledge to follow this course
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Familiarity with the C/C++ language is necessary
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The “High-level Synthesis for FPGA, part 1-combinational circuit” course is the prerequisite to this course.
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Download the “Vitis High-Level Synthesis User Guide (UG1399)” 
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document and have a look at its Table of Contents.