0 1 00:00:02,200 --> 00:00:08,050 Hello and welcome to this course: Digital System Design with High-Level Synthesis for FPGA: Sequential 1 2 00:00:08,050 --> 00:00:08,620 circuits. 2 3 00:00:11,090 --> 00:00:17,990 Are you familiar with C/C++ language and would like to work with FPGAs straightaway without spending 3 4 00:00:17,990 --> 00:00:23,480 months and months learning complex hardware description languages? Then welcome to this course. 4 5 00:00:26,040 --> 00:00:32,700 Are you a software or hardware student who is going to learn the latest technologies about FPGA without 5 6 00:00:32,700 --> 00:00:38,610 spending too much to learn low-level tedious logic optimisation techniques? Then welcome to this course. 6 7 00:00:41,250 --> 00:00:47,610 Are you a researcher with software or hardware background who is going to take his or her research to 7 8 00:00:47,610 --> 00:00:52,980 the next level by accelerating algorithms with FPGAs? Then welcome to this course. 8 9 00:00:56,690 --> 00:01:00,350 I am Mohammad. I have a PhD in Electronics and Computer Engineering. 9 10 00:01:00,610 --> 00:01:05,670 I have been teaching electronics and programming courses in several universities for more than 10 years. 10 11 00:01:06,040 --> 00:01:11,530 I have been doing research on reconfigurable computing for more than 20 years in different universities. 11 12 00:01:11,980 --> 00:01:19,420 I am the author of several conferences, journal and transaction papers published by IEE/IEEE 12 13 00:01:19,420 --> 00:01:20,110 and ACM. 13 14 00:01:20,290 --> 00:01:25,750 Also, I have developed several real applications on FPGAs during my research career. 14 15 00:01:27,110 --> 00:01:29,640 I’ll be your instructor and guide in this course. 15 16 00:01:30,110 --> 00:01:36,650 My first goal is to simplify the new technologies in reconfigurable computing to be used by students 16 17 00:01:36,650 --> 00:01:41,450 and researchers who have no or little background knowledge of FPGA. 17 18 00:01:42,510 --> 00:01:45,280 You may have heard that FPGA design is complicated, 18 19 00:01:45,420 --> 00:01:53,340 yes, it is, if you follow the traditional HDL design flow. However, high-level synthesis design flow 19 20 00:01:53,460 --> 00:01:59,280 makes the FPGA design easy and accessible for a large group of software and hardware engineers. 20 21 00:01:59,860 --> 00:02:04,350 It is my mission here to uncover the high-level synthesis design secrets 21 22 00:02:05,450 --> 00:02:08,360 with a straightforward and exciting approach. 22 23 00:02:13,240 --> 00:02:17,950 We are going to learn, discover and explore the topic of high-level synthesis, HLS. 23 24 00:02:18,420 --> 00:02:22,120 HLS is an entirely new hardware design technology. 24 25 00:02:22,690 --> 00:02:29,770 It is a set of hardware design-flow, optimisation techniques, coding styles, software tools, and 25 26 00:02:29,770 --> 00:02:31,000 debugging mechanisms. 26 27 00:02:31,390 --> 00:02:38,920 HLS is a technology that uses a high-level language such as C/C++ to hide all the traditional hardware 27 28 00:02:38,920 --> 00:02:41,470 design complexities from designers. 28 29 00:02:47,040 --> 00:02:52,080 So, if you are curious about high-level synthesis and don’t know where to start, 29 30 00:02:52,350 --> 00:02:53,550 welcome to this course series. 30 31 00:03:01,040 --> 00:03:08,030 If you are a university or college instructor, lecturer, or professor who wants to add an HLS flavour 31 32 00:03:08,300 --> 00:03:12,410 to the traditional HDL hardware design flow, then welcome to this course. 32 33 00:03:15,870 --> 00:03:21,960 If you want to show that you are clever enough to work with FPGA like a pro just in a couple of days, 33 34 00:03:22,110 --> 00:03:23,410 then welcome to this course. 34 35 00:03:26,300 --> 00:03:33,380 This course is based on the Xilinx HLS technology, including software toolsets and FPGA-based hardware 35 36 00:03:33,380 --> 00:03:34,080 platforms. 36 37 00:03:34,430 --> 00:03:42,200 The technology is well presented, and there are several examples, designs, applications, and supports around 37 38 00:03:42,200 --> 00:03:47,840 it, presented in this course and provided by Xilinx or the HLS community. 38 39 00:03:52,780 --> 00:03:59,410 The technology is already used by several companies to design many commercial devices, including NVIDIA® 39 40 00:03:59,440 --> 00:04:07,990 was able to simplify their code by 5X using HLS  HLS decreased design time by 50 per cent and 40 41 00:04:07,990 --> 00:04:11,750 overall development time, including verification, by 40 per cent. 41 42 00:04:12,010 --> 00:04:19,600 Google Develops WebM Video Decompression Hardware IP Using Technology Independent Sources and High-Level 42 43 00:04:19,600 --> 00:04:20,200 syntheses. 43 44 00:04:24,320 --> 00:04:30,590 In this course, I will use the Basys3 entry-level FPGA board to demonstrate several HLS design 44 45 00:04:30,590 --> 00:04:37,730 techniques. The Xilinx Vivado-HLx software toolset is used to develop logic designs starting from C/C++ 45 46 00:04:37,730 --> 00:04:39,290 code down to the FPGA. 46 47 00:04:43,800 --> 00:04:49,350 If you have a budget of a few hundred pounds and are going to learn very advanced topics on HLS 47 48 00:04:49,470 --> 00:04:55,800 and FPGA, then welcome to this course. You only need to spend a couple of hundred pounds to purchase 48 49 00:04:55,950 --> 00:05:01,750 the Xilinx Basys 3 FPGA board, and all the software tools are available for free via the Xilinx 49 50 00:05:01,830 --> 00:05:02,400 website. 50 51 00:05:06,020 --> 00:05:11,600 This course is the first of its kind that builds the HLS design flow and skills along with the 51 52 00:05:11,600 --> 00:05:14,790 digital logic hardware circuit concepts from scratch. 52 53 00:05:15,500 --> 00:05:22,400 This course is the second of a series on HLS in designing hardware modules and accelerating algorithms 53 54 00:05:22,520 --> 00:05:23,750 on a target FPGA. 54 55 00:05:25,630 --> 00:05:31,300 Whereas this course focuses on sequential circuits, the first course explains the HSL design techniques 55 56 00:05:31,480 --> 00:05:33,380 for describing combinational circuits. 56 57 00:05:33,760 --> 00:05:39,940 In addition, the other courses in the series will explain how to use advanced topics and optimisation 57 58 00:05:39,940 --> 00:05:45,310 techniques in HLS to design logic circuits and accelerate compute-intensive algorithms.