In the previous lecture, we design the leading one example using the HLS coding style. 1
Here, we are going to use the Vivado-HLS toolset to program the Basys 3 board and examine the example 2
in practice. 3
Firstly, download the design and testbench files available in the course resources part and save them 4
in a folder on your computer. Then, open the Vivado-HLS GUI. 5
Vivado-HLS opens with the welcome screen. 6
Click on the “Create New Project” option to open the project wizard Choose “leading_one-vhls” 7
as the project name and choose a proper path for the project files and then click Next. 8
In the “Add/Remove Files” step, insert leading_one as the Top-Function name. 9
Click on Add Files and go to the folder containing the design files and add them to the project and 10
then click next. 11
Now add the testbench files by clicking on the Add Files option and selecting the testbench files from 12
where you have saved them and then click Next. 13
Don’t forget to choose the Basys3 board as the target FPGA platform. 14
Let’s have a look at the design and testbench files. The design header file only includes the ap_int.h 15
header file to the design. 16
The design file contains the top function which has a nine-bit integer input argument and returns a 17
5-bit integer as the index of leading-one in the input argument. 18
The chain of if-else statements explained in the previous lecture implements the leading-one functionality. 19
Two pragmas define the design interfaces. 20
The testbench header file includes the design file and defines the design top-function prototype. 21
The testbench source file has the main() function, which implements the testbench functionality. Another function 22
called find_leading_one_golden is a software implementation of the 23
design which its results are compared against the hardware results. A for-loop in the main function generates 24
all the possible inputs and sends them to the design and compares the results with that of the golden 25
model. In the case of any discrepancy, 26
the status variable will get the value of -1. Later, 27
the main() function returns the status variable to determine the design failure or success. 28
Using the cout object; the code prints the input and result values on the screen for more examination. 29
Now we can perform the C-simulation to check the design functionality. 30
As can be seen, the testbench has checked all the possible outcomes successfully. 31
After performing the C-Simulation successfully, we are ready to call the high-level synthesis. 32
If we have a look at the synthesis report, we can see that the RTL design utilises 11 flip-flops, 33
which means the resulted hardware is not combinational. 34
To find out the reason 35
let’s have a look at the Analysis Perspective, here 36
we see that the design execution requires two steps which means most probably the design propagation 37
delay is bigger than the design clock period constraint considered during the project creation wizard. 38
To change that got back to the design perspective. Then 39
right-click 40
on the Solution1 folder and choose the “Solution Settings” option. 41
Now click on synthesis located on the left and on the right area change the period option from 10 42
to 20. 43
Now synthesise the code again. 44
This time you should get a combinational circuit which its propagation delay is 10.046ns. 45
10.046ns. 46
If you go to the Analysis Perspective, you will see that the design only requires one step to finish. 47
To make sure that the resulted RTL design is also correct. 48
We can perform RTL/C-cosimulation. 49
The results confirm that the design cycle-accurate simulation is correct. 50
Now we can generate the IP and ready to instantiate that in a Vivado-project. 51
In order to generate the final FPGA bitstream, Firstly, launch the Vivado Design Suite. From the Welcome 52
screen, click Create Project. Click Next on the first page of the Create a New Vivado Project wizard. 53
Choose “leading_one-vivado” as the project name and select a proper path 54
for the project, 55
and it is a good practice if you check the “Create Project Subdirector” option. 56
Click Next to move to the Project Type page of the wizard. 57
Select the “RTL Project” option. Select Do not specify sources at this time (if not the default). Click Next. On the Default 58
Part page, under Specify, click Boards and select the Basys3 board. 59
On the New Project Summary Page, click Finish to complete the new project setup. The Vivado workspace populates 60
and appears. 61
Click on the Create Block Design option under IP integrator in the Flow Navigator. In the resulting 62
dialog box accept the default name and press ok. 63
The Diagram window will be open. Right-click somewhere inside the diagram window and select the “IP 64
settings…” option. 65
In the setting dialog, select repository under the IP option on the left-hand side. Click on the plus 66
icon on the right and browse the folder of the Vivado-HLS project and press Select. 67
The vivado searches the path for any IP ands add that to the repository. 68
Then press ok to get back to the diagram window. 69
Then right-click somewhere inside the window and select the Add IP … option. 70
In the Search box type “leading_one” and then select “leading_one” and press Enter. 71
After successfully instantiating the IP in the design, 72
select its ports and press right-click and make them external. You can change their names with more 73
convenient options. 74
Now we should define a few physical constraints to connect the design ports to the FPGA pins. 75
For this purpose, go to the design view and right-click on the constraints folder and select Add Resources. 76
Make sure that the “Add or create constraints” option is selected in the Add sources dialog, 77
then click Next. Create a constraint file with the name of “leading_one”. 78
Copy the commented constraints for the Basys3 board provided by the vendor into the created file. 79
Uncomment nine switch constraints and assign them to the a input port of the design. 80
Then uncomment five lED constraints and assign them to the design output port. 81
Now select the “Generate Output Products” option. 82
After that Create HDL Wrapper. 83
Now you are ready to generate the FPGA bitstream. After generating the bitstream successfully, connect the 84
board to the computer and program the board. 85
Now lets examine the design on the board. 86
After programming the board, as all slide switches are at the zero position, all five output LEDs 87
are ON representing the number -1. 88
If we turn ON some of the slide switches, the index of the leading one is shown by the 5 output LEDs. 89
This lecture is the last in this section that explained the design concepts and techniques. So the 90
next lecture will give you a couple of hardware designs as exercises through which you review and master 91
the proposed techniques in this section. 92
This is our takeaway message. If you expect that an HLS C/C++ code describes a combinational circuit, 93
but the synthesis repost shows FF usage, then the propagation delay of the circuit is higher 94
than the design clock period constraint; 95
so increase the design clock period constraint and synthesise the code again to generate a fully 96
combinational circuit. 97
Now, the quiz question. 98
During C-simulation, print on the screen the design inputs and outputs by using cout object inside 99
the design file.