What is the hardware implementation corresponding to variables in an HLS code? In this lecture, 1
I am going to explain the hardware component corresponding to a variable considering its data type. 2
An HLS tool reads a code, optimises that, and then binds a hardware component to each element 3
in the optimised code. 4
During the optimisation process, some variables in the original code may be eliminated or merged by 5
other variables. 6
Also, the optimisation process can create new intermediate variables. 7
The survived variables after optimisation should be mapped to real hardware elements. 8
A synthesis tool usually implements a variable by a bunch of wires or memories. 9
Memories can be flip-flops, BRAMs, DDR, and other types of memories. 10
This implementation depends on the role of the variables in the code. 11
In this course, we are focusing on combinational circuits which don’t rely on memories. 12
Therefore, all variables in code should be mapped on a set of wires if they survive through the optimisation 13
process. 14
Throughout this course, I will explain how to write a code to be synthesised to a combinational circuit. 15
As an example, let’s consider this Boolean expression that combines four variables with OR operators. 16
A C/C++ function in HLS can implement this code. 17
The function has four input and one output arguments. 18
Then we can describe the expression and return the result. 19
Don’t forget to define hardware port interfaces. 20
Three OR gates can implement this expression. As can be seen, 21
all variables in the code have been implemented by wires in the hardware. 22
HLS tools optimise a code before its implementation. This implementation of our Boolean expression 23
has three levels of gates. 24
If we assume a delta delay for each gate then its propagation delay is 3delta. 25
This boolean expression can be optimised for performance, 26
thanks to the associativity of the OR operator. 27
The optimised implementation requires two levels of gates which its propagation delay would be 2delta. 28
Let’s have a look at the output of the vivado-HLS synthesising our boolean expression. 29
This picture is the analysis perspective in Vivado-HLS 30
after synthesising our boolean expression. It consists of 8 operations. 31
The first four operations read the inputs. Then two OR gates perform the OR operators 32
in parallel. The third OR gate combines the outputs of the first layer gates. 33
Finally, the last line returns the result. 34
Variables of floating-point data types also can be synthesised into wires or memories depending 35
on the involved operators and the design coding style. 36
Memory cells can be in the form of FFs, BRAMs, DDRs or other types of memories. 37
However, in combinational circuits which is the subject of this course, these variables are synthesised 38
into wires. 39
This arithmetic expression in which variables are of float data type can be synthesised by Vivado-HLS 40
into a combinational circuit. Similar to the Boolean expression example, 41
this C function can describe this mathematical equation. And the synthesised hardware uses three combinational 42
adders to implement this code. 43
Let’s have a look at the HLS output for this arithmetic expression. 44
I have created a Vivado-HLS project and written the HLS code in the design file. 45
In order to have a combinational logic, the clock period constraint should be higher than the circuit propagation 46
delay. For this purpose, go to the Solution Settings and set the clock period constraint to 200ns. 47
Now we are ready to synthesis the code. 48
After successfully synthesising the design, let’s have a look at the synthesis report. 49
The propagation delay of the circuit is about 88.970 ns 50
The circuit is combinational as it only uses the LUT resources and no memory cell is utilised 51
Also, all ports are simple wires without any specific interfaces. 52
Now we can generate the IP package. 53
Unfortunately, because of the Vivado-HLS GUI limitation to show the Analysis perspective 54
when the design clock period constraint is higher than 99ns, we cannot see the state diagram. But 55
we can have a look at the vivado RTL schematic to see the design structure. 56
To see the design RTL schematic, first, create a new Vivado project. Then create a block 57
design. To add our generated IP package, right-click anywhere inside the design area and select the 58
IP settings… option. Then goto repository and add the Vivado-HLS project folder to the repository 59
path. 60
Then right-click again anywhere inside the design area and select the Add IP option (or click on the plus 61
button in the middle). Find the name of the generated IP, which is addition4 and add that to the 62
design. 63
Make the design ports external and then create the HDL wrapper. 64
Now click on schematic option under RTL Analysis. 65
The RTL schematic view will be opened after a couple of seconds. 66
After expanding the design hierarchy, you will see three adders connecting together implementing 67
our design. 68
Using arbitrary bit-width signals, buses, and data is essential in a hardware design environment. 69
In the next lecture, I will explain how to use arbitrary precision data types in HLS. 70
These are our takeaway messages. The HLS optimisation process may eliminate variables in a code 71
or create new intermediate variables. The remaining variables after optimisation should be mapped to 72
real hardware elements. 73
A synthesis tool usually implements a variable by a bunch of wires or memories. 74
Now the quiz question. Find the dataflow graph of the following function after synthesis.