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Now that we are familiar with the testbench concepts and its coding style, we are ready to use the 
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Viviado-HLS IDE to perform the C and Co simulations in action. 
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Let’s consider this simple combinational circuit, which was explained in the previous section, as an 
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example to implement in HLS and test its correctness. This combinational circuit has three
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inputs and one output.
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So its truth table consists of eight rows. 
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We use this truth table as our golden model to compare with the design results.
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Open the corresponding Vivado-HLS project with the name of simple_combinational_circuit-vhls, 
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explained in the previous section.
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The project only contains the design source file.
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Create a testbench source file with the name of simple_combinational_circuit-tb.cpp
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under the Test Bench folder in the explorer view. Then create a testbench header file with the name 
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of simple_combinational_circuit-tb.h in the same folder. Add the design 
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top-function prototype in the testbench header file.
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Now in the testbench source file,
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write 
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the main function that returns an integer value.
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Define three boolean variables to pass values to the design inputs and a Boolean array with a size
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of 8 to keep all the possible design outputs. Define another Boolean array with a size of 8 
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to save all golden results extracted from the function truth table.
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Now, we should generate all the possible design input values. Three nested loops can do this task.
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Inside the nested loops, call the design function as shown in this code.
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Use another loop to compare the design outputs with the golden model values and report proper messages. 
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Don’t forget to update the status value according to the comparison results. 
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Now perform the C-simulation and have a look at the report to make sure that the design functionality 
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is correct.
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You can also perform the C-Simulation debugging process by choosing the Launch Debugger option. 
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This action opens the debug perspective 
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through which standard debugging features such as step execution, insert brake port are
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available.  Also, you can examine the variable contents through debugging. 
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To insert a breakpoint, you only need to click on the blue area next to each desired line. 
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After performing the C-Simulation successfully, we are allowed to run the HLS synthesis.
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Now we can perform the C/RTL Co-simulation to test the design cycle-accurate correctness. After finishing
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the simulation, check the report for the successful simulation. 
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You can also dump the design internal and port signal values in a file for showing them through a waveform 
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viewer. For this purpose, choose the proper option in the Co-Simulation Debug dialog. 
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After finishing the simulation, click on the waveform viewer icon, 
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which will open the Vivado for this purpose. 
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Select the design input and output ports to be shown in the waveform viewer. Then check the values. 
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This lecture is the last in this section that explained the design concepts and techniques. So the 
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next lecture will give you a couple of hardware designs as exercises through which you review and 
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master the proposed techniques in this section. 
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These are our takeaway messages. Through C-Simulation we can check the design functionality before
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HLS synthesis.
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Through RT/C Co-Simulation we check the cycle accuracy of the design.
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Also, we can dump the signal values through Co-simulation and examine them in the Vivado Waveform 
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viewer.
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Now, the quiz question.
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We know that the final hardware circuit is 
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combinational, but Why does the final waveform viewer contain reset, clock, start and other signals?