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How to evaluate our code at the early stages of the design flow and find the possible errors? Simulation
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is one of the common techniques to answer this question. And a testbench is an essential component 
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in the simulation process. 
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In this lecture, I will talk about the basic concepts behind a high-level C/C++ testbench and its 
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role in the simulation process.
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Verification is the process, along with the design flow to ensure the final design would satisfy
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the original features described in the specification. 
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These features can be functional such as output values or non-functional such as timing, security 
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and power consumption, to name a few.
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A verification process may check the correctness of the design output values, or it can verify and 
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demonstrate the amount of security or power consumption. 
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There are different techniques for verification including
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Simulation, in which a full software environment is used to evaluate the design description. In this approach, 
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a piece of software called testbench applies some input to the design and the design outputs are compared
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to with golden models.
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Emulation, in which the components of the whole system are imported into an environment to evaluate the 
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target design.  
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Formal verification, in which some mathematical approaches are used to prove the correctness of a give
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design description. Intelligent verification.
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The focus of this course is mainly on simulation-based verification. 
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A combinational design has n inputs and m outputs. The role of simulation is to apply all possible 
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inputs and check the outputs, comparing with a golden model provided by the design specification. 
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In an ideal case, the number of inputs is two to the power of n (2n), which should be generated during the 
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simulation.  A testbench is a piece of software that manages the simulation process. 
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A typical testbench consists of four tasks:
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Generate inputs, Apply inputs to the design, Apply inputs to the golden model, Compare the outputs
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of design with that of the golden model. A testbench first generates the inputs, then applies 
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them to the design and golden model and finally compares the results and reports any discrepancy among
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them.
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Now that we get the testbench big picture, What is the testbench design flow in HLS? The next lecture 
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handles this question.
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These are our takeaway messages: Simulation is the verification technique provided by HLS tools
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A testbench should perform four main tasks: Generate input, Call the design, Execute the golden model
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and compare the design results with that of the golden model.
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Now the quiz question. Assume a hardware design has five binary inputs, how many input vectors should 
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a test bench generate to check the functionality of the design?