0
1
00:00:01,000 --> 00:00:06,790
One of the main tasks at the early stages of a hardware design development flow is evaluating the 
1

2
00:00:06,790 --> 00:00:14,020
code for functional correctness, quality of results and the level of performance. Simulation is one 
2

3
00:00:14,020 --> 00:00:18,040
of the techniques that provides this evaluation process. 
3

4
00:00:18,430 --> 00:00:23,390
This section explains the basic ideas behind the simulation process in HLS.
4

5
00:00:25,530 --> 00:00:32,580
In a typical code simulation, we apply an input to the code under development, execute the code and 
5

6
00:00:32,580 --> 00:00:40,050
examine the results for functional and timing correctness or evaluating non-functional features such 
6

7
00:00:40,050 --> 00:00:42,200
as security, and power consumption.  
7

8
00:00:44,630 --> 00:00:53,000
In this section, you will learn:  C software simulation in HLS, What a testbench is, Hardware/Software 
8

9
00:00:53,000 --> 00:00:54,080
Co-Simulation in HLS.
9

10
00:00:56,160 --> 00:01:03,780
This section consists of five lectures.  The current lecture talks about the section goals and its structure.
10

11
00:01:04,830 --> 00:01:11,940
The next section defines the verification and simulation in hardware design. Lecture 3 explains how
11

12
00:01:11,940 --> 00:01:14,490
develop a test bench code in HLS.
12

13
00:01:15,180 --> 00:01:19,280
The fourth lecture demonstrates how to use the Xilinx 
13

14
00:01:19,290 --> 00:01:23,310
Vivado-HLS toolset to implement a test bench along with design.
14

15
00:01:23,370 --> 00:01:29,910
The last section gives a few exercises to review and master the test bench design techniques.
15

16
00:01:31,580 --> 00:01:37,400
How to evaluate our code at the early stages of the design flow and find the possible errors?
16

17
00:01:38,890 --> 00:01:45,430
In the next section, first, I will list possible approaches for design verification, and then I focus 
17

18
00:01:45,430 --> 00:01:48,510
on the simulation process and its different stages. 
18

19
00:01:50,470 --> 00:01:55,760
These are our takeaway messages: Simulation is used to evaluate an HLS design.
19

20
00:01:56,530 --> 00:01:59,530
It can significantly increase your productivity