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After translating our simple combinational circuit design in HLS into the equivalent hardware IP, we should 
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generate the FPGA bitstream and program the basys3 board.
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For this purpose, run the Xilinx Vivado Suite software.
Create a new project and name its 
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simple_combinational_circuit-vivado. Also, choose the Basys3 board as the 
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target FPGA.
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Now, Click on the Create Block Design link and accept the default design name.
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Right-click somewhere inside the design area and select IP setting option from the drop-down menu. 
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Then select the repository option and click on the plus sign. Choose the Viviado-HLS project folder
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created in the previous lecture and press, OK.
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Then right-click anywhere inside the design area and select Add IP. On the search area, write 
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simple_combinational_circuit and add the IP to the design area.
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Now select the design ports. You can do that by holding the Ctrl key while clicking on the ports. 
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Then press the right-click and choose the Make External option. 
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You can also change the ports’ names to make them more convenient. 
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Now, we should connect the design ports to some pins on the FPGA. This can be done by adding a few
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constraints.
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For this purpose, go to the Source view and right-click on the Constraints folder and then select the
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Add Sources option.
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Make sure in the Add Source dialog box, the Add or create constraints is selected. Then in the add or 
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create constraints, click on Create File and choose the simple_combinational_circuit 
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as the file name.
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Now we can copy the Basys3 board constraints provided by its vendor. 
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Then uncomment and modify the required constraints. 
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We need three switches to provide binary values for our design inputs, and one LED to show the design output.
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Now we are almost ready for bitstream generation.
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But before that, right-click on the design option in the Source view and run the Generate Output
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products option.
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After that, right-click again on the design option in the Source view and choose the Create HDL
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Wrapper… option.
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Now we are ready to generate the bitstream.
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After generating the bitstream, we can connect the board to our computer and reconfigure the FPGA 
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and examine the design.
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Up to now, we managed to design a simple combinational circuit and run that on the target FPGA. In 
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our HLS design description, the C/C++ functions play important roles.
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The next section explains the structure of functions in a design description and their relationship 
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with the structure of the generated hardware module. 
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These are our takeaway messages. As well as the design RTL-IP, we should add the design physical constraints 
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to the Vivado project. To program the FPGA board, Connect the board to the computer, Turn on 
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the board, Use the Vivado IDE to program the board.
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Now the quiz question. Use the design RTL IP generated in the previous lecture quiz question and 
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program the Basys3 board and explore the design.