After being familiar with designing a simple conventional circuit using Etchells, we should now use
it before the actual design environment in practice and implement our design in this lecture.
We are going to use the actual aside to synthesize a simple logic circuit explained in the previous
lecture and review some practical tips for designing computational circuits.
First run designing second HLS and create a new project.
Name the project simple underscore combination's underscore circuit, dash futureless, then choose
a proper location for the project.
Name the top function as simple, underscore combination's underscore circuit and choose the basis three
board as a target FPGA.
Creating a design fine under the sauce folder in the explorer of you on the left hand side, name it
as simple, underscore, combination, underscore circuit that CPB.
Let's try the design example code that we started in the previous lecture.
It has three binary inputs and a binary output.
Now we are ready to synthesize the code and examine the report.
So let's perform that synthesis.
As you can see, the design propagation delay is about zero point nine seven eight nanoseconds, also
the result of the hardware is a combination of circuit as it doesn't utilize any memory cell and its
ports are just simple wires representing the function arguments.
To better understand the result of the hard work structure, let's have a look at the analysis perspective
for this purpose, switch to this perspective by clicking on the corresponding icon on the right hand
side.
Windows in this perspective are configured to support the analysis of synthesis results, you can use
this perspective only when the Atlas synthesis complete successfully.
The analysis perspective interactively provides greater details, the left of the center, Paynesville
Shuls operations under control of states in the center site design control states are the internal state
that high level centers as to casual operations into Kalac cycles notice that a combination of circuits
should perform all its tasks in a single state.
That's can be our design performs its logical function in a single state denoted by zero.
By selecting each operation, this perspective shows the timing and data dependencies between the selected
operation and its predecessors and successors.
Here we have Terry Reid operations corresponding to the three input arguments in the design, one and
get.
They're not is implemented by unexcelled gate.
And an old gate, finally, there is a right operation to return the result.
After understanding the synthesized hardware structure, now we should generate the RTL IP and prepare
for logic synthesis for this purpose.
You should go back to the synthesis perspective and click on the corresponding icon.
Now that we have generated our design RTL IP, we should generate its corresponding F.J. with the story
and examine that on the basis three wars.
This would be the goal of the next election.
This is our takeaway message, the analysis perspective in Nevada, HLS provides greater detail of the
design, including the design structure, timing and resource binding.
Now, the quiz question generate an IP corresponding to this simple combination of acerca.