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After understanding the combinational logic and its associated propagation delay, the next question 
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is: How can we describe a combinational circuit in HLS?
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Let’s take a simple combinational circuit and describe that in HLS. Consider this logic circuit 
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comprised of three gates. 
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The functionality can be described by this logical expression. In order to describe this expression in 
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C/C++, we have two options.
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We can either use C/C++ logical operators or C/C++ bitwise operators. Whereas logical operators are applied
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to one-bit logic that can be 1/0 representing true/false, the bitwise operators are applied
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to a multiple-bit value. 
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I will explain how to use bitwise operators later in this course.
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Therefore, we can use either of these expressions in HLS to describe our circuit example.
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We need a function to describe our combinational circuit.
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The function should have three input and one output arguments. We define a pointer variable for the 
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output argument. Then we should write the logical expression describing the circuit functionality.
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After that, we have to define the argument interfaces as well as the function block interface.  As
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we are using wires to carry logic values, we use ap_none or ap_ctrl_none as the interface 
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modes.
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Now we are ready to synthesis the code.
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After doing the synthesis successfully, the tool gives us a thorough report in which three parts are important 
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for us now: Timing, Utilisation, and Interface parts. The timing part is more suitable for sequential 
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circuits.
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However, at the moment we are interested in the third column denoted as “Estimated”.
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This number is an estimation of the design propagation delay.
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More details about this estimation approach will be described in the “Digital System Design with High-
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Level Synthesis in FPGA: Sequential Circuit” course. 
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So, the propagation delay of our design is about 0.978 ns.
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The second part reports the resource utilisation. This part reports an estimation of the number of 
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resources that will be used for implementing the design.
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The report has five columns.
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Three of them include memory resources (which are BRAM_18k, FF, and URAM). 
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As we are designing combinational circuits, these resources shouldn’t be used, and their utilisation
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should be zero.
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The other two columns that are DSP48E and LUT can be used to implement a combinational 
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circuit. The DSP48E is used for mathematical operators, especially for floating-point data 
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types.
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The LUTs are used for implementing logical expressions and gates. 
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Notice that our design has only used 6 LUTs.
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The last part is about argument interfaces which its table has six columns.
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The first one is the name of the hardware RTL port. 
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The second column denotes the direction of the hardware signals. 
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The number of bits associated with each port is defined in the third column.
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The next column determines the corresponding interface mode. 
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The fifth column denotes the name of the arguments in the top-function.
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Finally, the last column shows the type of argument in c, whether it is a scalar or a pointer.
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In the next lecture, I will practically show how to use the Xilinx Vivado-HLS to synthesis 
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our simple combinational circuit.
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These are our takeaway messages. The HLS report of a combinational circuit synthesised by vivado-HLS  
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Should not utilise any memory elements.
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Also, it should not have any clock port in the interface part.
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Now the quiz question. Complete this code by defining the port interfaces using HLS pragmas.