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In this lecture, I will take an n-bit binary adder to represent the process of the propagation delay 
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calculation.
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This circuit is a full-adder design that receives two data bits, an input carry bit, and then after a delay generates
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the sum and the output carry bits.
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carry bits.
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There is a total of 9 paths from inputs to outputs. And If we assume that the delay of an XOR gate
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is 2ns and other gates require 1ns to generate their outputs, 
then delays
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of the paths from a or b to the s output are 4ns. Tthe delay of the cin input to the s output 
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is 2ns.
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The delays of other paths are also 2ns. 
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So, the longest path in the circuit requires 4ns to propagate the changes on the inputs to 
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the outputs, which means, the output of this full adder should generally be used 4ns after 
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changes on its inputs.
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An N-bit binary adder can be designed by simply connecting N full-adders sequentially such that 
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the output carry bit of a full-adder feeds the next full-adder input carry. This design usually called 
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the ripple carry adder. This adder utilises the least amount of hardware of all binary adders, but it is the slowest.
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Each full-adder in the ripple carry adder structure has three paths for data propagation. 
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From a & b inputs to the s output, from carry input to the s output, and from carry input to the carry 
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output.
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Let’s trace the data along these paths. Let’s assume that the input numbers are available at 0ns.
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Then after 2ns, the impact of the first bit full adder carry bit appears on s0 and c0. 
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Then after 4ns, the input data changes the values on s0 to sn-1 outputs.
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However, only the s0 and s1 values are valid, and others will be changed later.
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At 6ns, S2 and C2 are valid and finally after 2n ns the last sum and carry
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bits are valid.
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Two paths determine the last sum and carry bits, and both have 2N ns delay. Therefore, the
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propagation delay of the whole design is 2N ns.
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After understanding the logic design structures and their propagation delay concept. 
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Their HLS-based design techniques and approaches would be our next topic.
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Also, it is obvious that it is not easy for us to calculate the propagation delay for all circuits,
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especially if they are described in a high-level language such as C/C++. 
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Now the question is: How can we use the Vivado-HLS tool to estimate this delay? In the next 
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lecture, 
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I explain how to use Vivado-HLS to describe a logic circuit and estimate its propagation delay.
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This is our takeaway message. Serially connected modules in hardware increase the corresponding propagation 
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delay.
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Now the quiz for this lecture. I have slightly changed the structure of the full-adder and the gates 
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propagation delays in this quiz. 
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Now, what is the propagation delay of the n-bit adder utilises this full-adder?