How long does it take for the outputs of a combinational circuit to reflect the input changes? To answer 1
this question, 2
I will introduce you to the propagation delay in combinational circuits. 3
Real logic gates do not react instantaneously to the inputs, and therefore any changes on the inputs 4
of a logic gate need some time to have an impact on the gate output. 5
This time is called the gate propagation delay and may change from one gate to the other. 6
Also, propagation delay may be varying for different changes on the gate inputs. 7
However, in this course, we only consider a single propagation delay for each gate which can be considered 8
as the average of all gate’s propagation delays. 9
Let’s consider this NAND gate. We use t_p to show its propagation delay. 10
Now, assume a is zero, b is 1 then the output c would be 1. 11
Now let’s consider a transition from 0 to 1 on the a input and the b input remains intact. 12
Then, based on the NAND gate functionality, the c output should change from 1 to 0. 13
However, it happens after a delay. 14
During this delay, the gate output is not valid and shouldn’t be used for any further computation or 15
decision making. 16
Now, if we have a state change from 1 to 0 on the b input, we can see its impact on the output 17
after the gate propagation delay. Again during this delay, the output is not valid. 18
The propagation delay is also defined for a combinational logic circuit. There are usually several 19
propagation paths from inputs to outputs in a combinational circuit. 20
Each path has its own propagating delay. 21
The path with the maximum delay is called the critical path, and its delay is considered as the circuit 22
delay. 23
Let’s consider this logic circuit. 24
It consists of four inputs, two outputs and two types of operators. 25
Let’s assume the delay of the add operator is 2ns, and that of the multiplier is 3ns. 26
Path P1 includes two operators g1 and g2. It starts from the a input and ends at the f output. 27
Therefore, its associated delay is 2+2=4ns. 28
The delay of the path from the b input to the f output is also 4ns. 29
The next path starts at input c and passes through the g2 operator, and its delay is 2 ns. The 30
delay of the third path is 3ns as it starts at a and passes through the g4 operator. 31
The final paths start at c or d inputs pass through g3 and g4 operators. Therefore their 32
propagation 33
delays are 5nsec. 34
The P4 path is the critical path as it causes the longest delay. 35
So its delay is considered as the circuit propagation delay. 36
To summerise, I should say that it takes time for the outputs of a combinational circuit to reflect 37
the input state changes. This time is called propagation delay, which is defined by the critical path 38
in the circuit. 39
This delay also determines the performance of the design and its response time. 40
One of our main goal in HLS is reducing this delay and decreasing the design response time. 41
The impact of design strategy on the circuit propagation delay is our next topic. In the next step, 42
using n example I will show how the sequential execution of several hardware modules can increase 43
the propagation delay and reduce the design performance. 44
These are our takeaway messages. Outputs of a logic circuit are not generally valid as soon as changes 45
on inputs happen. Outputs will be valid and used after the circuit propagation delay elapses. 46
Now the first quiz for this lecture. Let’s assume the following circuit in which all gates have the 47
same propagation delay denoted by t_d. Find the output signal diagram for these input values. 48
In the second quiz, Let’s assume the full-adder circuit in which all gates have the same propagation 49
delay denoted by t_d. Find the propagation delay of this circuit.