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How long does it take for the outputs of a combinational circuit to reflect the input changes? To answer 
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this question, 
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I will introduce you to the propagation delay in combinational circuits.
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Real logic gates do not react instantaneously to the inputs, and therefore any changes on the inputs 
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of a logic gate need some time to have an impact on the gate output.
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This time is called the gate propagation delay and may change from one gate to the other. 
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Also, propagation delay may be varying for different changes on the gate inputs. 
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However, in this course, we only consider a single propagation delay for each gate which can be considered
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as the average of all gate’s propagation delays.
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Let’s consider this NAND gate. We use t_p to show its propagation delay. 
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Now, assume a is zero, b is 1 then the output c would be 1. 
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Now let’s consider a transition from 0 to 1 on the a input and the b input remains intact. 
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Then, based on the NAND gate functionality, the c output should change from 1 to 0. 
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However, it happens after a delay. 
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During this delay, the gate output is not valid and shouldn’t be used for any further computation or
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decision making.
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Now, if we have a state change from 1 to 0 on the b input, we can see its impact on the output
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after the gate propagation delay. Again during this delay, the output is not valid. 
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The propagation delay is also defined for a combinational logic circuit. There are usually several 
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propagation paths from inputs to outputs in a combinational circuit.
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Each path has its own propagating delay. 
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The path with the maximum delay is called the critical path, and its delay is considered as the circuit 
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delay.
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Let’s consider this logic circuit. 
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It consists of four inputs, two outputs and two types of operators.
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Let’s assume the delay of the add operator is 2ns, and that of the multiplier is 3ns.  
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Path P1 includes two operators g1 and g2. It starts from the a input and ends at the f output. 
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Therefore, its associated delay is 2+2=4ns.
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The delay of the path from the b input to the f output is also 4ns.
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The next path starts at input c and passes through the g2 operator, and its delay is 2 ns. The
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delay of the third path is 3ns as it starts at a and passes through the g4 operator.
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The final paths start at c or d inputs pass through g3 and g4 operators. Therefore their 
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propagation
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delays are 5nsec.
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The P4 path is the critical path as it causes the longest delay. 
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So its delay is considered as the circuit propagation delay.
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To summerise, I should say that it takes time for the outputs of a combinational circuit to reflect 
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the input state changes. This time is called propagation delay, which is defined by the critical path
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in the circuit.
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This delay also determines the performance of the design and its response time. 
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One of our main goal in HLS is reducing this delay and decreasing the design response time.
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The impact of design strategy on the circuit propagation delay is our next topic. In the next step, 
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using n example I will show how the sequential execution of several hardware modules can increase
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the propagation delay and reduce the design performance.
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These are our takeaway messages. Outputs of a logic circuit are not generally valid as soon as changes 
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on inputs happen. Outputs will be valid and used after the circuit propagation delay elapses. 
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Now the first quiz for this lecture. Let’s assume the following circuit in which all gates have the 
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same propagation delay denoted by t_d. Find the output signal diagram for these input values.
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In the second quiz, Let’s assume the full-adder circuit in which all gates have the same propagation 
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delay denoted by t_d. Find the propagation delay of this circuit.