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In the previous lecture, we designed the traffic light controller in HLS. In this lecture, we use the 
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Vivado-Hlx toolset to map our controller on the Basys3 board.  
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Firstly, create a new Vivado-HLS project and name it traffic_light-vhls. Then, choose 
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a proper path for the new project. After that.
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choose the traffic_light as the design top function name.
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Don’t forget to choose the Basys3 board as the target FPGA platform.
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Download the design files attached to this lecture and save it inside the created Vivado-HLS project
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folder (or any other desired folder).
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Right-click on the source folder in the Explorer View in the Vivado-HLS IDE and select the “Add Files…” option. 
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Then go to the folder where you saved the traffic-light files and select the two “traffic_light.cpp”
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and “traffic_light.h” files and add them to the project.
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Open the files and examine them. 
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The traffic_light.h
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is almost empty. 
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I have considered that just for future usage.  
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The traffic_light.cpp file contains five subfunctions describing the five rules 
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that I explained in the previous lecture. And also the design top function.
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The design top function invokes the subfunctions and generates the outputs. 
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It also has the function argument interfaces. 
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Now we can perform the HLS synthesis process. The synthesis report shows that the circuit delay is about  
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2.934 ns. And the generated hardware is combinational as it uses only LUTs 
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without any memory cells.
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In addition, the top function arguments are the only hardware ports. 
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After successfully synthesising the code, we can generate the corresponding RTL-IP. Now we should 
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instantiate the IP inside a Vivado project to generate the final FPGA bitstream.
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Create a new vivado project with the name of “traffic_light-vivado”.
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Don’t forget to choose the Basys3 board as the target FPGA platform.
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Create a new block design by clicking on the “Create Block Design” under IP Integrator in the Flow Navigator 
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view.
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Right-click somewhere inside the Diagram area and select the “IP setting…” option.
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Then select the Repository option under IP in the list of project setting options on the left.
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press the plus side and go to the traffic light, all do this project folder.
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This process makes our traffic light controller RTL-IP available to the vivado design.
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Now we should instantiate the controller IP. For this purpose,
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right-click 
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somewhere inside the Diagram area and select the Add  IP … option. Search for the traffic_light 
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IP and add that to the design.
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The design should have four 1-bit input ports and two 1-bit output ports.  Make all the ports external. 
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Then you can rename the ports to have more suitable names. 
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Now we should connect them to the FPGA pins. For this purpose, we need to define a set of constraints. 
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You can do that by pressing the right-click on the design_1 under the “Design Sources”
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in the Sources view and select the “Add Sources” option. 
In the “Add Sources” dialog, 
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make sure that the “Add or create constraints” option is selected then press next. Then create 
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a constraint file with the name of 
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traffic_light.
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Double click on the created file under the Constraints folder in the Source view.  Now copy the commented 
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constraints provided by the Board vendor and uncomment the required ones. As the design has four 1-bit 
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inputs and two 1-bit outputs, 
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we need constraints for four switches and two LEDs.  Modify the ports name in the constraints according to 
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the ports name in the design. 
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Now before generating the FPGA bitstream, First we should generate the output products and then create 
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the HDL wrapper. 
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After that, we can generate the FPGA bitstream.
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To program the board, connect that to your computer and turn that on. You should see the red power light 
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illuminates.
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Now in the Vivado-IDE click on the Open Hardware option under the Program and Debug in the Flow Navigator 
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View.
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Then click on the Open Target link and select the Auto Connect option. The Vivado IDE automatically detects 
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the board and shows that in the hardware list. 
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If you cannot see the board and the FPGA, check the board connected to your computer or turn on the board 
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if you have forgotten. 
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Now click on the Program device link to configure the FPGA. After programming the board successfully, 
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the DONE green light should illuminate. 
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Now we are ready to examine our controller. 
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Each switch corresponds to a sensor, and each led represents a traffic light.  Play with sensors and 
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check the lights and make sure your design responds correctly.  
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This lecture is the last in this section that explained the design concepts and techniques. So the 
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next lecture will give you a couple of hardware designs as exercises to be implemented by HLS design 
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flow.
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These are our takeaway messages.
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The name of ports in constraints should be exactly the same as the name of the corresponding port 
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in the design.
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In the current Vivado-HLS description of a design, only arguments in the top-function require attached 
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interfaces. So, the Sub-function arguments don’t need any interfaces as they won’t be synthesised into hardware 
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parts.
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Now the quiz question.
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Find the resource utilization of the final design in Vivado. For this purpose, in the Flow Navigator, click 
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on “ImplementationOpen Implemented DesignReport Utilization”