0
1
00:00:00,650 --> 00:00:05,930
In the previous section, we studied the basic input/output techniques in a logic circuit and how to
1

2
00:00:05,930 --> 00:00:10,220
implement them in HLS. The logic circuit functionality was simple,
2

3
00:00:10,550 --> 00:00:12,850
just a couple of wires. In this section, 
3

4
00:00:13,010 --> 00:00:15,620
I am going to focus on the logic circuit functionality. 
4

5
00:00:15,980 --> 00:00:21,560
The logic circuits in this section use the same input/output mechanisms, but instead, they process the
5

6
00:00:21,560 --> 00:00:24,260
input data to generate some new output data.
6

7
00:00:26,180 --> 00:00:32,660
A typical logic circuit applies an algorithm onto the input data and generates the output data. These algorithms 
7

8
00:00:32,660 --> 00:00:40,820
can be A simple arithmetic function,  A data transmission, A coding conversion, Or a complex task 
8

9
00:00:40,820 --> 00:00:43,370
such as AI training or inference process.
9

10
00:00:45,780 --> 00:00:51,510
This section focuses on combinational circuits which their outputs are functions of their inputs at 
10

11
00:00:51,510 --> 00:00:56,680
any specific time and the inputs are stable during the process of generating outputs. 
11

12
00:00:57,210 --> 00:01:03,420
These circuits can describe a wide range of applications from arithmetic and logical operators to data 
12

13
00:01:03,420 --> 00:01:05,600
transformation and transmission.
13

14
00:01:07,900 --> 00:01:13,300
This section consists of 13 lectures. This lecture, as the first one introduces the section.
14

15
00:01:14,760 --> 00:01:21,120
The second lecture defines combinational circuits and their features. 
Logic gates as the basic building 
15

16
00:01:21,120 --> 00:01:22,070
blocks of combinational 
16

17
00:01:22,080 --> 00:01:26,210
circuits are introduced in lecture three. Gates and combinational
17

18
00:01:26,210 --> 00:01:31,230
circuits require some time to process the input values and generate the output.
18

19
00:01:31,560 --> 00:01:35,550
This processing time is called propagation delay, which is explained in lecture four.
19

20
00:01:38,180 --> 00:01:44,540
In Lecture five, I will take the binary adder as an instructive example to clarify some concepts in designing 
20

21
00:01:44,540 --> 00:01:50,320
a combinational circuit. How to describe a combinational circuit in HLS is the subject of Lecture 
21

22
00:01:50,340 --> 00:01:50,740
six.
22

23
00:01:51,710 --> 00:01:57,560
Lecture seven uses the Xilinx Vivado-HLS to synthesise a combinational circuit to its equivalent RTL 
23

24
00:01:57,560 --> 00:01:58,130
description.
24

25
00:01:59,300 --> 00:02:05,060
Generating the final FPGA bitstream of a combinational circuit would be the subject of the eighth lecture.
25

26
00:02:06,050 --> 00:02:12,710
C/C++ functions are the main components in describing hardware circuits is HLS. Lecture nine will 
26

27
00:02:12,710 --> 00:02:18,590
explain the structure of these functions and their relations with the final hardware modules.
Lecture 
27

28
00:02:18,590 --> 00:02:23,990
10 will introduce the dataflow graph concept as the main modelling technique describing a combinational 
28

29
00:02:23,990 --> 00:02:27,630
circuit. To put all the explained concepts together in action,
29

30
00:02:27,860 --> 00:02:33,790
I will explain how to design a combinational circuit for a simple traffic-light controller through lectures
30

31
00:02:33,800 --> 00:02:34,700
11 and 12.
31

32
00:02:35,620 --> 00:02:41,800
The last lecture will give a couple of design examples as exercises to review and master all the design 
32

33
00:02:41,800 --> 00:02:43,720
concepts explained throughout this section.
