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In the previous lecture, we generated the RTL-IP of our LED controller.
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Now how can we integrate that in a Vivado project to generate the final FPGA bitstream?
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In this lecture, I will address this question.
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Firstly, run the Xilinx Vivado Suite.
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Then create a new project with the name of “basic_input_output-vivado”
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Finally, select the Basys3 board as the target FPGA platform.
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Create a new block design in the Flow Navigator by clicking on “Create Block Design” under the IP Integrator 
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heading.
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Right-click in the diagram and select “IP settings…”. A separate settings dialog opens, select the Repository 
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under IP in the left-hand side options. Start to add the generated basic-input-output RTL-IP by clicking
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on the plus button. Then select the corresponding vivado-HLS folder 
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Vivado will search the folder and add the IP to its repository and make that available for design 
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integration.
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Now, right-click in the diagram and select 
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Add IP. A searchable IP Catalog opens. 
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Find the basic_input_output IP and add to the diagram.
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Select the input port and make that external. You can change its name from inputs_0 to 
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SW. For this purpose, while the input port is selected, go to the name filed in External Port Properties.
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Do a similar thing to the output port and change its name to LED.
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Now we should connect the design ports inside the FPGA to the FPGA pins. Adding a few constraints to
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the design, will do that. For this purpose, 
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go to the source view and create a new constraint file by pressing the right-click on the Constraints 
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folder and selecting the “Add Sources…”
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In the Add Source Dialog, make sure that the “Add or create constraints” option is selected. Then press Next.
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Click on the Create File and choose a file name such as “basic_input_output” and 
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press the OK and Finish buttons. Open the constraint xdc file by double-clicking on the file name.
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Copy and paste the list of commented constraints provided by the Basys3 board vendor. 
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We should uncomment eight switches and eight LEDs. As the design port 
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names are the same as names used in the constraint 
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file,  we don’t need to do any other changes. 
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We are almost ready to generate the bitstream. However, before that, we should do two other tasks. 
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Firstly, go to the design view and right-click on design_1 and select the “Generate
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Output Products…” option. 
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Then right-click again on the design_1 and select the “Create HDL Wrapper” option.
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Now click on the Generate Bitstream option in the Flow Navigator View.
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After the bitstream is generated, we can program the Basys3 board. For this purpose, connect the board to 
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your computer and turn that on.  Open the hardware manager by clicking on the corresponding icon under
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the PROGRAM AND DEBUG in the flow navigator view.
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Then open the target, 
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the Viviado should detect the board automatically 
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if not check your connections and make sure that the board is ON.
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Then click on the Program device link and examine the board. 
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This lecture is the last in this section that explained the design concepts and techniques. So the 
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next lecture will give you a couple of hardware designs to be implemented by HLS design flow.
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This is our takeaway message. To program the target FPGA through JTAG connection, 	Connect the board
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to the computer, Then turn on the board, Finally, use the vivado design suite to program the board.
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Now the quiz for this lecture,
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Integrate the RTL-IP generated in the last lecture quiz question into a Vivado project and generate 
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the FPGA bitstream. Then program the board and examine the outputs.