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After having a big picture of the design steps in the Xilinx Vivado suite HLx toolset, we should 
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know the specific tool that performs each step.
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Vivado design suite-HLx consists of two main software tools: Vivado-HLS and Vivado. 
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The HLS design flow 
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starts with Vivado-HLS software. 
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This software gets your design description in C/C++ and translates it into the equivalent HDL description.
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The Vivado-HLS 
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software performs five subtasks including 
Design capture, C-Simulation, HLS synthesis, Co-Simulation 
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and Package generation
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The generated package or IP should be imported into Vivado design suite software for logic synthesis 
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and then bitstream generation.
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Vivado consists of five steps including: Design capture, RTL simulation, Logic synthesis
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Implementation, and finally Bitstream generation
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The generated bitstream can be used to program the target FPGA.
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Let’s have a close look at the Vivado-HLS IDE.
After running the Vivado-HLS software, 
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an eclipse-based IDE appears on the screen. 
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The whole design is defined under a project which its structure is represented in the Explorer view. 
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The main part of the project structure is the source and testbench folders where you can add a new source file 
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or delete an existing file from the project.
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A proper editor allows you to write your code and find the typos.
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All the HLS tasks can be invoked by clicking on the proper icon on the toolbar. Four main icons are corresponding 
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to C-simulation, Synthesis, Co-simulation, Export RTL (or IP generator)
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The generated IP by the Vivado-HLS should be imported into the vivado design suite 
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for logic synthesis. Vivado-IDE provides a project-based process. 
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You can use Vivado IDE to perform all tasks from design definition to the bitstream generation. 
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The flow navigator pane contains a list of all these tasks.
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The top section in the flow navigator is for changing the project settingssuch as adding source 
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files,  defining the parameters of target 
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FPGAs, simulation, synthesis, implementation, bitstream and lots of other features that we explain 
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parts of them along the course.
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The second section “IP integrator” is used for defining the design space and integrating the generated 
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IP by Vivado-HLS into the design. The RTL simulation is accessible in the third section.
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Sections 4 to seven are used for RTL analysis, logic synthesis, Implementation and bitstream generation.
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Now the question is, How can we install our software and hardware components and prepare our lab 
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environment? In the next lecture, 
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I will answer this question.
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These are the takeaway messages from this video
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To use C/C++ language to design hardware, targeting Xilinx FPGAs, we should use two different software 
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tools.
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Vivado-HLS and Vivado.
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The Vivado-HLS converts the C/C++ description to the equivalent HDL code and the Vivado receives the HDL code 
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and generates the final FPGA bitstream.
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Now the quiz questions, 1- What are the design tasks in the Xilinx Vivado-HLS software?
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2- What are the design tasks in the Xilinx Vivado software?