0 1 00:00:01,050 --> 00:00:07,710 Xilinx evaluation is a toolset that we are using throughout this course here, I'm going to briefly 1 2 00:00:07,710 --> 00:00:09,420 explain some of their features. 2 3 00:00:10,540 --> 00:00:15,580 More details of each feature will be described whenever we use them along the course. 3 4 00:00:18,280 --> 00:00:25,630 Xilinx Vivado-HLx consists of several tools that are used to describe, simulate, debug, and synthesise 4 5 00:00:25,720 --> 00:00:30,810 a design at a different level of abstractions to be implemented on the Xilinx FPGAs. 5 6 00:00:31,450 --> 00:00:33,790 Each tool performs a specific task. 6 7 00:00:34,000 --> 00:00:37,890 In this slide, I am going to give you a big picture of the design flow. 7 8 00:00:38,080 --> 00:00:43,930 The main goal of this software tool is converting a hardware design description into the final FPGA 8 9 00:00:43,930 --> 00:00:44,670 configuration. 9 10 00:00:45,310 --> 00:00:52,360 Several languages, including VHDL/Verilog, SystemC, C/C++ and OpenCL can be used to 10 11 00:00:52,360 --> 00:00:53,890 describe a hardware design. 11 12 00:00:54,160 --> 00:00:58,470 In this course, we focus on C/C++ as a high-level description language. 12 13 00:00:59,050 --> 00:01:05,890 The first step is the design capture in which the design description is verified, and possible errors 13 14 00:01:05,890 --> 00:01:06,790 are reported. 14 15 00:01:07,540 --> 00:01:13,210 The capture process mainly focuses on the linguistic syntax and semantics of the hardware modules, 15 16 00:01:13,720 --> 00:01:16,480 connections among them and their ports. 16 17 00:01:18,200 --> 00:01:21,050 After writing the code, simulation is an optional 17 18 00:01:21,860 --> 00:01:27,980 but essential step. Simulation is one of the main debugging techniques that designers spend most 18 19 00:01:27,980 --> 00:01:31,460 of their time (almost 70%) to verify their codes. 19 20 00:01:32,430 --> 00:01:38,340 There are different levels of simulation provided by Vivado-HLx such as high-level C simulation, 20 21 00:01:38,580 --> 00:01:45,090 low-level HDL simulation and hardware-software co-simulation. Whereas the high-level C simulation can be 21 22 00:01:45,090 --> 00:01:47,710 used for verifying the functionality of a design, 22 23 00:01:47,970 --> 00:01:53,950 the low-level HDL simulation can be used for functional correctness as well as cycle accurate verification. 23 24 00:01:54,990 --> 00:02:01,590 The co-simulation integrates the software and the hardware parts in order to bring the cycle-accurate verification 24 25 00:02:01,740 --> 00:02:03,890 into the high-level synthesis design flow. 25 26 00:02:04,850 --> 00:02:12,910 In this course, we rely on high-level C simulation and co-simulation to debug our designs. Code analysis is 26 27 00:02:12,910 --> 00:02:18,830 the primary step before applying synthesis optimisation techniques. Data and control dependencies, 27 28 00:02:19,130 --> 00:02:23,820 timing and hierarchy analyses are the most important tasks in this step. 28 29 00:02:24,110 --> 00:02:29,310 These tasks help the next step to apply synthesis optimisations more efficiently. 29 30 00:02:29,420 --> 00:02:35,630 Note that, developing the design code to ease the code analysis can improve the final design performance. 30 31 00:02:37,630 --> 00:02:44,260 In HLS design flow, understanding the data and control dependencies among statements plays a crucial 31 32 00:02:44,260 --> 00:02:46,630 role in developing an efficient code. 32 33 00:02:47,630 --> 00:02:53,300 Therefore, throughout this course, I will try to easily explain these dependencies and different code 33 34 00:02:53,300 --> 00:03:00,200 development techniques to help code analysis step. Synthesis is the most important part of the Vivado-HLx 34 35 00:03:00,200 --> 00:03:01,760 design suite. 35 36 00:03:02,480 --> 00:03:10,370 Generally, two levels of synthesis are available: high-level synthesis (HLS) and logic synthesis (LS). 36 37 00:03:11,300 --> 00:03:18,950 While HLS translates a C/C++/SystemC/OpenCL description of a design into its equivalent 37 38 00:03:18,950 --> 00:03:21,020 RTL, 38 39 00:03:21,020 --> 00:03:25,700 LS converts the RTL description into a netlist of logic gates. 39 40 00:03:25,700 --> 00:03:32,780 High-level synthesis is the main subject of this course, and I will talk about some of its techniques 40 41 00:03:32,900 --> 00:03:36,350 used for digital system design in future lectures. 41 42 00:03:36,920 --> 00:03:42,680 The implementation step uses the FPGA library and building-blocks to implement the netlist generated 42 43 00:03:42,680 --> 00:03:43,910 by the synthesis step. 43 44 00:03:44,540 --> 00:03:50,390 This step performs all tasks necessary to place and route the netlist onto device resources. 44 45 00:03:51,020 --> 00:03:53,870 The last step is the bitstream generation and programming. 45 46 00:03:54,710 --> 00:04:00,920 This step generates the configuration file (also known as a bitstream) that can be used to program 46 47 00:04:00,920 --> 00:04:01,610 an FPGA. 47 48 00:04:05,710 --> 00:04:09,480 Concentrating on the HLS design flow will be our next step. 48 49 00:04:12,510 --> 00:04:18,480 These are the takeaway messages: The Xilinx Vivado-HLX toolset is used for developing a hardware 49 50 00:04:18,480 --> 00:04:20,640 circuit for the Xilinx FPGAs 50 51 00:04:21,810 --> 00:04:28,850 In our course, we use this toolset to convert a C/C++ description of a design into the FPGA bitstream file 51 52 00:04:28,860 --> 00:04:29,120 file. 52 53 00:04:31,380 --> 00:04:36,990 Now the quiz question. What is the difference between C-simulation and co-simulation in HLS?