0 1 00:00:01,330 --> 00:00:06,940 What element inside an FPGA can save data temporarily to be used later in the design? In addition 1 2 00:00:06,940 --> 00:00:13,150 to the LUT, FPGAs have several small temporary memories to save the results of LUTs in order 2 3 00:00:13,150 --> 00:00:15,310 to implement sequential logic circuits. 3 4 00:00:15,760 --> 00:00:20,770 These memories which called flip-flops are similar to the registers in a CPU hardware architecture. 4 5 00:00:22,410 --> 00:00:28,890 A flip-flop is one of the basic storage units within an FPGA fabric. Flip-Flops are registers that can save 5 6 00:00:28,890 --> 00:00:30,800 data being used later in the design. 6 7 00:00:31,620 --> 00:00:35,940 These resisters can also act as a distributed memory space in the FPGA. 7 8 00:00:36,780 --> 00:00:43,260 LUTs enable implementing the combinational logic on an FPGA. Combinational logics are digital 8 9 00:00:43,260 --> 00:00:48,230 circuits that their outputs are functions of the present values of their inputs only. 9 10 00:00:49,020 --> 00:00:52,440 Therefore, LUTs sometimes called function generators. 10 11 00:00:53,350 --> 00:00:59,320 Adding FF to FPGAs enables them to implement sequential logic. The outputs of a sequential logic 11 12 00:00:59,320 --> 00:01:05,080 depend not only on the present value on the inputs but also on the history of their values. 12 13 00:01:06,350 --> 00:01:12,380 Any digital circuits can be implemented by LUTs and FFs. However, to increase the performance 13 14 00:01:12,380 --> 00:01:21,530 of arithmetic logics, FPGAs usually add basic logical gates (including AND, OR, and NOT) to their structure in order 14 15 00:01:21,530 --> 00:01:25,560 to facilitate the carry calculation involved in these types of operations. 15 16 00:01:26,000 --> 00:01:32,060 More details about the logic circuit of these gates are beyond the scope of this course, and their 16 17 00:01:32,060 --> 00:01:34,280 understanding is not necessary for learning HLS. 17 18 00:01:34,380 --> 00:01:40,430 A collection of LUTs, FFs and logic gates are packed together and create a 18 19 00:01:40,430 --> 00:01:42,290 slice in FPGA structure. 19 20 00:01:42,830 --> 00:01:48,490 This figure shows a Slice in Xilinx 7-series, which is one of the most common Xilinx FPGA families. 20 21 00:01:49,190 --> 00:01:52,550 It has three layers of elements, 6-input LUTs 21 22 00:01:53,870 --> 00:01:58,580 Arithmetic carry logic circuits, FFs and multiplexers 22 23 00:02:00,280 --> 00:02:05,950 A set of two Slices and a switch matrix to connect the slices to the routing on the FPGA is called a 23 24 00:02:05,950 --> 00:02:11,230 Configurable Logic Block or CLB for short. An FPGA can be considered as a 2D 24 25 00:02:11,230 --> 00:02:17,380 array of CLBs. This figure shows a 2D array of CLBs connected through a connection network. 25 26 00:02:17,830 --> 00:02:20,740 The connection network consists of wires and switches. 26 27 00:02:20,950 --> 00:02:26,560 The switches are configurable to provide paths to connect different CLBs in order to create complex 27 28 00:02:26,560 --> 00:02:27,430 logic functions. 28 29 00:02:28,120 --> 00:02:34,840 A group of I/O paths (shown around the FPGA structure in this figure) enables the internal logic to communicate 29 30 00:02:34,840 --> 00:02:37,510 with the outside world to receive or send data. 30 31 00:02:38,390 --> 00:02:44,890 The communication can be between FPGA and external memories, FPGA and external peripherals or FPGA 31 32 00:02:44,890 --> 00:02:45,590 and CPUs. 32 33 00:02:46,910 --> 00:02:52,760 Any arithmetic operation can be implemented on this traditional FPGA structure using the corresponding 33 34 00:02:52,760 --> 00:02:54,270 bit-level logical expression. 34 35 00:02:55,280 --> 00:03:00,620 However, the final circuits won’t be efficient, especially for floating-point arithmetic operators. 35 36 00:03:01,100 --> 00:03:07,820 New FPGA structures add additional computational and data storage blocks that increase the computational 36 37 00:03:07,820 --> 00:03:10,060 density and efficiency of the device. 37 38 00:03:10,370 --> 00:03:15,530 These additional elements include: Embedded blocks of memories as data storage 38 39 00:03:15,890 --> 00:03:18,410 These memories also called BRAM or Block RAM. 39 40 00:03:19,850 --> 00:03:26,960 Phase-locked loops (PLLs) for driving the FPGA fabric at different clock rates. High-speed serial transceivers. 40 41 00:03:28,580 --> 00:03:35,690 Off-chip memory controllers. Digital Signal Processing (DSP) elements that enable implementing efficient 41 42 00:03:35,690 --> 00:03:43,130 floating-point arithmetic operations. Embedded multi-core CPU. Analog/Digital Converter. 42 43 00:03:44,350 --> 00:03:49,540 Now that we have a big picture of the FPGA structure, we should connect that to a couple of peripherals 43 44 00:03:49,540 --> 00:03:51,980 on a board to communicate with the environment. 44 45 00:03:52,120 --> 00:03:58,360 So, our question for the next lecture is What is the structure of the FPGA-based evaluation board that 45 46 00:03:58,360 --> 00:04:00,520 we are going to use along this course? 46 47 00:04:01,770 --> 00:04:08,910 These are our takeaway messages: An FPGA has logical, storage and additional elements. Logical elements 47 48 00:04:08,910 --> 00:04:11,550 can be used for logical and arithmetic operations 48 49 00:04:11,910 --> 00:04:15,930 Storage elements can be used as registers or blocks of memories 49 50 00:04:16,200 --> 00:04:22,110 Additional elements can be used for floating-point arithmetic operations, serial communication or other 50 51 00:04:22,110 --> 00:04:23,130 complex functions. 51 52 00:04:24,660 --> 00:04:29,040 Now the quiz questions 1) What are the two main memory resources in an FPGA? 52 53 00:04:30,180 --> 00:04:33,330 2) Name two elements that can implement arithmetic operators?