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How does a LUT work in an FPGA? LUTs are the main building blocks of FPGAs that 
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implement combination logics. Here, 
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I am going to explain the idea behind the LUTs.
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A Look-up table has a configuration memory that keeps all the possible outputs of a logic function. 
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It also has a set of inputs to select the proper cell in the memory corresponding to the inputs logic 
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state.
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But how is this selection process possible? 
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Here I am going to quickly explain the idea behind this selection by introducing the concept of multiplexers.
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One of the key components inside a look-up table is a multiplexer. A simple multiplexer has two data inputs, 
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one data output and a control signal, also known as select input. A multiplexer acts as a switch and connects 
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one of its data inputs to the output, based on the value on its select input.
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In this figure, if c (the select input) is 0, then the a input is connected to the d output. 
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Otherwise, the b input is connected to the output.
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After introducing the multiplexer, lets put that into the LUT structure. A conceptual structure 
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of a LUT can be considered as a collection of memory cells connected to a set of multiplexers. 
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This is the conceptual structure of a 2-input look-up table which consists of 4 memory cells and three 
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multiplexers. if both a and b are 0 then cell 0 is connected to the output
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if a is 1 and b is 0 then cell 1 is connected to the output
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if a is 0 and b is 1 then cell 2 is connected to the output. if both a and b are 1 then  cell 
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3 is connected to the output
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Having this big picture of a LUT, implementing a given 2-input logical function is as simple 
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as copying the last column of the corresponding truth table into the LUT memory cells.
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For example, to configure a 2-input LUT to implement an AND gate, we should set the cells 
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by the logic values of 0 0 0 1.
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A look-up table usually has a couple of inputs and outputs. The number of LUT inputs determines 
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its capacity. 
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For example, a 5-input look-up table can implement any logical function with 5 or fewer variables. 
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For implementing a logical function 
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with more than five variables, you should use more than one 5-input LUT.
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For example, a 6-input LUT can be created by using two 5-input LUTs and a . 
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multiplexer
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After understanding the LUT structure, the question is, What elements inside an FPGA can save 
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data temporarily to be used later in the design?
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The role of temporary memory cells is crucial in FPGA, and they are used almost in all real applications. 
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I will explain the purpose of these types of memory in the next video.
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This is the takeaway message from this lecture: The multiplexer concept is used to connect LUT’s 
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reconfigurable memory cells to the output.
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Now the quiz question. Determine the data path in the following LUT and the value of the output
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if a=0, b=1, c=1;