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Firstly, the question for this lecture. 
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Do we need to learn the internal structure of an FPGA to implement a circuit or an algorithm in HLS?
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The internal structure of an FPGA is invisible to the users, so design tools take care of them. 
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However, having a basic knowledge of the internal structure and different resources in the FPGA helps 
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designers to better understand the tools’ report in order to provide an efficient design.
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More details of the FPGA architecture are explained throughout the course whenever we are going to use 
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them.
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Let’s start with creating a big picture of a typical FPGA structure.
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Conceptually, an FPGA comprises of two layers: application and configuration layers.
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The application layer contains all the hardware modules that can be configured and connected together to implement an
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algorithm or a function. 
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After configuring this layer, we can apply the input data and get the generated outputs. 
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The configuration later consists of a set of memory cells used to configure the application layer modules. 
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The configuration data saved in this layer is call bitstream and is generated by synthesis tools. 
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The main role of an FPGA synthesis tool is converting a design description into an FPGA bitstream. This process 
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requires several optimisations and code transformation tasks. 
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The generated bitstream is used for configuring the FPGA. Then the configured FPGA can be used in a real 
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application to perform the desired algorithms or functions. 
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Traditionally, an FPGA is a collection of the following building blocks: Loop-up-tables 
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(LUTs): which are used to implement logic operations
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Flip-Flops (FFs): these are registers (or small temporary memories) to save the LUTs’ outputs.
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Connection network: which connects resources on an FPGA together. Input/Output (I/O) pads: to get data 
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in and out of the FPGA
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Let’s talk about lookup tables: A LUT can be configured to implement a logical function 
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or expression. A logical unction is an expression that only contains logical operators, which are AND, 
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OR and NOT. The AND and OR operators are binary, which means they receive two operands (also known as variables 
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or inputs). 
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The NOT operator is unary, which means it applies on a single variable or input. A truth table
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can represent the functionality of each gate. 
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This table contains the gate’s output values for all combinations of its input logic values.
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To implement a logical expression, a typical lookup table keeps the output values for all combination 
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of the expression’s inputs. For example, this is an AND logic or gate. A lookup table that implements 
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this gate keeps all the values in the last column of the gate truth table. 
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Then it needs two inputs to address each value.
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This logical expression has three inputs. Then its truth table has  8 entries. A lookup table
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should keep all the values in the last column. And it needs three inputs to distinguish among them.
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How does a LUT work in an FPGA?
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The next video copes with this question.
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The takeaway messages are: A traditional FPGA consists of LUTs, FFs, I/O pins 
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and finally a network connecting these elements
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All these components are reconfigurable. 
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As the quiz question, I want you to find the LUT content for the following logic expression.