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Despite all the benefits of the FPGA technology, FPGA-based design can be a real challenge. 
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Implementing logic circuits and computing algorithms on an FPGA requires its own design flow and 
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techniques.
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This lecture briefly explains different levels of abstractions in the FPGA design flow. 
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Low-level design flow based on logic gates such as AND, OR and NOT was the first design flow for implementing 
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simple logic circuits on FPGAs. 
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Using this approach, designers can implement simple circuits on small FPGAs. 
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With the increase in the number of resources available on new FPGAs and their high design capacity, 
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Register Transfer Level (RTL) design approach became a standard which still is used by many designers. 
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VHDL and Verilog are the two widely adopted RTL languages among the designers in industry and academia. 
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The high demand for computational power and the unique features of advanced FPGAs have motivated 
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designers to propose a higher-level design approach to map complex algorithms on an FPGA with less effort. 
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Therefore, High-level synthesis (HLS) design techniques, in which software languages such as C/C++ 
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are used for design description is proposed. In this design approach, 
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the HLS toolsets are responsible for automatically synthesising the C description into an efficient 
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hardware circuit. 
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Hardware Design Languages (HDLs) such as VHDL and Verilog are the standard way for describing a design at 
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gate-level or RTL. These languages are used to describe the functionality and timing of a hardware 
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circuit.
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There is also a close relationship between the language statements and the hardware resources available 
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on an FPGA.
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These features make the design process tedious as designers should have in-depth knowledge about the 
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hardware timing and resources. The HDL languages are usually compared with the assembly languages 
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in software.
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The HLS uses high-level software-based languages that are used to describe the design functionality. And 
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it is the responsibility of the HLS toolset to extract the timing and hardware resources, automatically. 
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This approach helps the designers with low hardware knowledge to map complex algorithms and applications 
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on a given FPGA.
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Therefore, rapid advances in FPGA applications have been possible with using High-Level Synthesis techniques.
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HLS is pretty hot these days, and it is a topic which is definitely here to stay.
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HLS is a set of coding styles, optimisation techniques, and synthesis tools to map a software function 
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onto a hardware platform such as FPGA. 
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Notice that using HLS with specific coding styles and optimisation directives enables us to 
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map almost any logical or mathematical function on a given FPGA. 
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Several companies are using HLS techniques to design their hardware products including Nvidia 
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in designing Tegra embedded GPU, Google in building VP9 encoder/decoder, Qualcomm in image processing
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AMD in designing microprocessors,  ST Micro in implementing H.265.
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Both FPGAs and CPUs can be used to implement logical and computational functions. But what are their 
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differences? In the following lecture, 
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I briefly explain the underlying difference between these two computing platforms.
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The takeaway messages from this lecture are: HLS is a new hardware design approach, and it is a 
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topic which is definitely here to stay. HLS is the preferable design approach to map a complex algorithm 
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on a given FPGA. HLS can also be used for designing traditional logic circuits
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Now, the quiz of this lecture, 
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Which design level is more suitable for implementing a machine-learning algorithm on an FPGA? And Why?
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Gate level based on VHDL language,  RTL based on Verilog language,  HLS based on C/C++