1 00:00:01,850 --> 00:00:07,270 In this lecture, we will use the Weimar dialect toolset to run the simple calculator on the basis what 2 00:00:07,910 --> 00:00:12,170 you can find the project source files in the resources folder attached to this lecture. 3 00:00:15,200 --> 00:00:23,120 Firstly, your view new the Atlas project with simple underscore calculator dash, listen and consider 4 00:00:23,120 --> 00:00:25,880 the Basis three evaluation board and the Target FPGA. 5 00:00:28,880 --> 00:00:32,300 Then create design and test bench source and halophiles. 6 00:00:46,740 --> 00:00:52,970 Open the are fine then include the AP underscore in that file and define a few arbitrary production 7 00:00:52,980 --> 00:00:59,010 data types, then defined the Southern segment code for the minus sign and when all segments are off. 8 00:00:59,900 --> 00:01:06,200 Also define a constant array containing all the seven segment codes, four digits from zero to F.. 9 00:01:07,820 --> 00:01:14,840 Open the design Sourcefire defining of function, which receives five inputs and generates two outputs 10 00:01:15,470 --> 00:01:16,880 at the port interfaces. 11 00:01:20,050 --> 00:01:27,250 Call it three functions explained in the previous lecture that our operations extract digits and display 12 00:01:27,250 --> 00:01:27,790 digits. 13 00:01:30,220 --> 00:01:34,270 Finally, send all the inputs from slide switches to daylilies. 14 00:01:38,430 --> 00:01:43,890 Notice the way of concatenated for inputs and unused bit that is assigned to zero. 15 00:01:45,970 --> 00:01:50,320 Here, we should explicitly use the typecast AP underscore in one. 16 00:01:51,780 --> 00:01:58,560 Otherwise, the stool concatenated A and B and feels the rest of the bits with zero, which is not desire. 17 00:01:59,400 --> 00:02:02,010 Now we should define the three functions. 18 00:02:02,520 --> 00:02:04,650 We create a source file for each function. 19 00:02:07,240 --> 00:02:13,000 Create a file called operations that sweep under the design source folder, then write the operations 20 00:02:13,000 --> 00:02:18,310 function code, which contains a switch case statement to select the proper operation here. 21 00:02:18,640 --> 00:02:24,790 I have used a 10 bit sine arbitrary precision data type for the result as I am expecting to consider 22 00:02:24,790 --> 00:02:27,420 more operations later, such as multiplication. 23 00:02:28,120 --> 00:02:32,200 You can use fewer bits for the result if you wish anyway. 24 00:02:32,380 --> 00:02:36,970 Detlor synthesis tool optimises the hardware and removes old unused bits. 25 00:02:39,140 --> 00:02:45,740 Create a file called extract underscored digits that slip under the design source folder, now copied 26 00:02:45,740 --> 00:02:47,930 extract, underscored digits of function code. 27 00:02:47,930 --> 00:02:54,230 Here, the code defines division by a constant number as a sole function which cannot be inline during 28 00:02:54,230 --> 00:02:55,580 the synthesis optimization. 29 00:02:56,150 --> 00:03:02,210 The function body detects the result sinus and extracts the three digits according to the display mode, 30 00:03:02,360 --> 00:03:03,890 which can be hexadecimal. 31 00:03:13,480 --> 00:03:18,730 For implementing the last stop function, create a new file under the design source folder with the 32 00:03:18,730 --> 00:03:21,160 name of display underscore digits that. 33 00:03:22,330 --> 00:03:25,380 Now copy the corresponding code into the created file. 34 00:03:25,900 --> 00:03:27,730 You can find the project source files. 35 00:03:27,850 --> 00:03:31,690 Are the resources attached to this lecture or the course GitHub site. 36 00:03:32,970 --> 00:03:38,010 The code contains a function called seven, underscore Sigmon, underscore Daejeon, underscore code 37 00:03:38,190 --> 00:03:40,770 that returns the code corresponding to a received digit. 38 00:03:41,770 --> 00:03:46,960 The code also contains the function that sends the proper data and value to the seven segments. 39 00:03:49,450 --> 00:03:55,240 For example, if select underscored digit is zero zero zero one, which means the user has pressed the 40 00:03:55,240 --> 00:04:01,660 left push button, then the function will send the first digit code to the first down segment and activate 41 00:04:01,660 --> 00:04:04,810 that by the one one one zero control value. 42 00:04:05,590 --> 00:04:09,280 The code does the same for the other digits just for the sine digit. 43 00:04:09,280 --> 00:04:14,950 It first checks that these three, which represents the sign and then sends a proper seven segment code. 44 00:04:15,730 --> 00:04:19,510 If none of the push buttons is pressed, then all seven segments are of. 45 00:04:20,750 --> 00:04:25,310 Now, let's add the prototypes of the defined functions into the design Gadaffi. 46 00:04:28,960 --> 00:04:34,280 We should now develop the test flights, going to the test bench header file and include the design 47 00:04:34,280 --> 00:04:40,010 header file and other design top function prototype in the source that speechify defined the main function. 48 00:04:40,480 --> 00:04:44,430 Firstly, we need to declare a couple of variables to be used later. 49 00:04:45,220 --> 00:04:51,030 Then we use five minutes and loops to go over all the possible input values by using the following. 50 00:04:51,070 --> 00:04:54,120 This is we should prepare the design top function arguments. 51 00:04:55,510 --> 00:05:01,420 Notice that as I assume that the users only press one push button at the time the selected. 52 00:05:01,420 --> 00:05:04,150 You should have only one bit with the value of one. 53 00:05:04,630 --> 00:05:09,070 Therefore, I have used the left shift operator to implement this restriction. 54 00:05:11,140 --> 00:05:15,830 Then we should apply the data to the design and its equivalents, software implementation. 55 00:05:16,420 --> 00:05:18,720 So let's define the software implementation. 56 00:05:20,130 --> 00:05:26,040 Create a new source fine with the name of simple underscore calculator, underscore software that sweep 57 00:05:26,070 --> 00:05:30,540 under the test bench folder, then copy the function code into the file. 58 00:05:38,120 --> 00:05:43,480 Finally, in the test bench, main function, comparative results and report any possible error. 59 00:05:51,320 --> 00:05:55,190 Now, we are ready for this simulation after performing this simulation. 60 00:05:55,370 --> 00:05:58,310 The report confirms the design functionality correctness. 61 00:06:04,860 --> 00:06:10,320 After doing this simulation successfully, you can perform the high level synthesis, the design report 62 00:06:10,320 --> 00:06:15,330 shows that the resultant Archil hardware has used flipflops and is not a combination of. 63 00:06:16,340 --> 00:06:19,790 To find the problem, let's have a look at the analysis perspective. 64 00:06:25,990 --> 00:06:32,200 That's can be seen, the design execution requires eight steps to finish, therefore the short design 65 00:06:32,200 --> 00:06:34,920 clock period constraint can be the source of the problem. 66 00:06:35,500 --> 00:06:37,720 Let's increase the design clock period constrain. 67 00:06:39,280 --> 00:06:45,790 As a devout Catholic period, constraint is 10 and our design requires eight steps to complete, let's 68 00:06:45,790 --> 00:06:48,990 change that from 10 to 80 and synthesize the code again. 69 00:07:03,250 --> 00:07:04,960 Now, the design is fully confidential. 70 00:07:06,630 --> 00:07:12,240 To make sure that they generated RTL design is correct, let's perform the RTL sequence simulation. 71 00:07:35,780 --> 00:07:41,900 After finishing the simulation successfully, we can package the design into an article IP to be used 72 00:07:41,900 --> 00:07:46,820 later in interview are the Project for Logic Synthesis and if BGB this third generation. 73 00:07:48,990 --> 00:07:55,770 To generate FPGA bitstream, we need a the project, so let's create a the project with the name of 74 00:07:55,770 --> 00:08:01,740 simple underscore calculator dashboard and consider the basis three as a target FPGA platform. 75 00:08:14,980 --> 00:08:21,820 Then create a block design in order to use our design IP, we should add that to the repository. 76 00:08:41,870 --> 00:08:49,160 Now we can instantiate the IP and add that to our design, make the ports external and change the names 77 00:08:49,160 --> 00:08:49,940 if you wish. 78 00:09:33,720 --> 00:09:39,500 Now, let's define the constraints you can find them in the project source files attached to this lecture. 79 00:10:24,710 --> 00:10:30,470 Before generating the bitstream first, we should perform the generate output product task. 80 00:10:31,510 --> 00:10:32,860 And credentialled rapper. 81 00:11:01,360 --> 00:11:07,180 After generating the bitstream successfully, we can program the board and examine the design functionality 82 00:11:07,180 --> 00:11:07,680 on the board.