1 00:00:01,780 --> 00:00:06,670 In the previous lectures, we talked about the intelligent addition, subtraction and multiplication 2 00:00:06,670 --> 00:00:11,620 in us and how to synthesize them in divide us into different hardware structures. 3 00:00:13,480 --> 00:00:19,390 In this lecture, I'm going to cover the integer division and modulus operators initialised as these 4 00:00:19,390 --> 00:00:25,330 operators require special attention when it comes to synthesizing them into combination or circuits. 5 00:00:27,740 --> 00:00:33,110 What is the integer division return is the caution of two integer values, the modulus returns the remainder 6 00:00:33,110 --> 00:00:34,250 of the integer division. 7 00:00:35,850 --> 00:00:43,020 For example, if you consider these two numbers that are four hundred and eighty seven and 32, then 8 00:00:43,020 --> 00:00:45,990 they integer division is 15 and they're modulars is seven. 9 00:00:48,240 --> 00:00:55,020 Integer division by a constant value is a special case in which the divisor is a fixed number, synthesizing 10 00:00:55,020 --> 00:01:00,690 an integer division by a constant value generates a combination of circuit by default if the clock period 11 00:01:00,690 --> 00:01:05,250 is larger than the circuit propagation delay, as can be seen in this regard. 12 00:01:05,580 --> 00:01:07,230 Let's report the propagation. 13 00:01:07,230 --> 00:01:13,170 DeLay is about fifteen point five four four nanoseconds and the implementation utilizes for the Espy's 14 00:01:13,350 --> 00:01:16,380 and 197 lookup tables. 15 00:01:17,580 --> 00:01:23,340 We can add resource constraint to the area, able to buy the division operator to the defense corps, 16 00:01:23,640 --> 00:01:26,830 which is a pipeline for implementation of the signed integer division. 17 00:01:27,420 --> 00:01:30,840 In this case, the results won't be a combination or circuit. 18 00:01:31,140 --> 00:01:38,310 And we can see the design utilizes five percent of flipflop memory cells and the IP has to extra input 19 00:01:38,310 --> 00:01:44,860 signals which are AP underscore sialic and AP underscore Oreste representing the design and research 20 00:01:44,890 --> 00:01:45,720 respectively. 21 00:01:47,760 --> 00:01:53,610 We want HLA synthesis synthesisers, the integer division by a variable into a pipeline circuit by default, 22 00:01:54,060 --> 00:01:59,850 and if we add the resource constrained to bind the operator to the D and score, the result would also 23 00:01:59,850 --> 00:02:00,600 be a pipeline. 24 00:02:04,200 --> 00:02:08,790 Synthesizing the modulus operator results in a pipeline circuit in all cases. 25 00:02:10,750 --> 00:02:16,510 However, if you want to synthesize the modulus of a number by a constant value into a combination of 26 00:02:16,510 --> 00:02:19,720 circuit, we can use its equivalent equation like this. 27 00:02:20,620 --> 00:02:26,170 Let's say that in practice, using the five other cells to learn if you're coding a science for developing 28 00:02:26,170 --> 00:02:27,230 a combination or circuit. 29 00:02:29,490 --> 00:02:35,580 First, let's create a new evaluation project with the name of integer underscore division, underscore 30 00:02:35,580 --> 00:02:36,570 Modulus Daneshvar. 31 00:02:38,280 --> 00:02:42,750 And choose integer, underscore division, underscore modulars as a top function name. 32 00:02:43,260 --> 00:02:46,530 Don't forget to choose the basis three and the target FPGA. 33 00:02:50,720 --> 00:02:53,900 Now, we should create a new file to describe the design function. 34 00:03:02,230 --> 00:03:05,080 First of all, let's define an integer constant value. 35 00:03:08,200 --> 00:03:14,230 The design top function receives an integer input denoted by a unretire as an integer output denoted 36 00:03:14,230 --> 00:03:14,710 by R. 37 00:03:16,870 --> 00:03:18,900 The return value is a modulus. 38 00:03:22,940 --> 00:03:25,070 Now, we should add port interfaces. 39 00:03:26,170 --> 00:03:27,400 Let's synthesize the code. 40 00:03:31,220 --> 00:03:37,670 The synthesis report shows that the design utilizes flipflops and has two extra ports which are Klok. 41 00:03:38,720 --> 00:03:43,940 Let's have a look at the analysis perspective to get more information from the inside of the synthesis 42 00:03:43,940 --> 00:03:44,510 process. 43 00:03:44,900 --> 00:03:49,250 As can be seen, it uses its frame operator to implement the modulus. 44 00:03:49,520 --> 00:03:54,660 And this operator is implemented by pipeline circuit, which has about 35 stages. 45 00:03:55,340 --> 00:04:01,040 Now let's implement the modulus functionality with division by a constant number using this expression. 46 00:04:02,790 --> 00:04:08,520 To more understand the synthesis tool behavior, I will follow a step by step process to implement this 47 00:04:08,520 --> 00:04:09,110 expression. 48 00:04:09,540 --> 00:04:12,810 So let's consider only the division by a constant number. 49 00:04:22,210 --> 00:04:26,160 If we synthesize the code, there is also this combination of. 50 00:04:28,390 --> 00:04:34,390 Now, if you have a look at the analysis perspective, the division by a constant number is implemented 51 00:04:34,390 --> 00:04:40,960 by basic arithmetic operators look, suspend expression and multiply the division by the constant number. 52 00:04:53,550 --> 00:04:58,150 After synthesizing the code, we will realize that the output circuit is not computational. 53 00:04:58,830 --> 00:05:00,580 Let's check the analysis perspective. 54 00:05:01,170 --> 00:05:06,260 We see that the sentence is optimization process has used the SRM operator to implement the expression 55 00:05:07,890 --> 00:05:13,920 we should find a way to stop the optimization process from using this operator for this purpose. 56 00:05:14,070 --> 00:05:16,690 I define a function that implements the division. 57 00:05:17,250 --> 00:05:22,740 However, as they want to tell a synthesis tool automatically in lines all the small functions, we 58 00:05:22,740 --> 00:05:26,640 expect to see the SRM operator again in the synthesis report. 59 00:05:57,560 --> 00:06:02,720 Let's prevent this automatic enlightening by using the inline directive with the off option. 60 00:06:16,250 --> 00:06:20,150 Now, if you synthesize the code, the resulting circuit would be a combination. 61 00:06:49,470 --> 00:06:52,830 We just need to complete the expression and synthesize again. 62 00:07:11,640 --> 00:07:15,980 The new synthesis report confirms that the generator, the hardware is a combination. 63 00:07:33,130 --> 00:07:38,800 This lecture is a class in this section that explains the design concepts and techniques, so the next 64 00:07:38,800 --> 00:07:44,620 lecture will give you a couple of harder designs and exercises through which you review and master the 65 00:07:44,620 --> 00:07:46,480 proposed techniques in this section. 66 00:07:48,460 --> 00:07:55,420 This will take him a message I proper directives to the code can prevent the synthesis tool from applying 67 00:07:55,420 --> 00:07:59,800 some different optimization techniques and generate the desired RTL hardware. 68 00:08:00,890 --> 00:08:06,710 Now, the quiz question compared to the propagation delay of the first implementation for the modulus 69 00:08:06,710 --> 00:08:11,990 operator with that of the last one, which was implemented by a combination of circuit.