1 00:00:01,690 --> 00:00:07,840 In addition to the clock period, constrained resource constraints also have a direct impact on the 2 00:00:08,260 --> 00:00:14,470 syntheses floor to create a combination of acerca before introducing the resource constraints and adding 3 00:00:14,470 --> 00:00:15,760 them to our designs. 4 00:00:16,030 --> 00:00:20,380 This lecture briefly explains the computational resources in an advanced FPGA. 5 00:00:21,470 --> 00:00:26,610 Traditionally, FPGA is where using logic gates to describe arithmetic expressions. 6 00:00:27,200 --> 00:00:31,430 This solution is adequate for applications with a few arithmetic operations. 7 00:00:31,460 --> 00:00:37,490 However, applications with complex computations require more efficient implementation techniques to 8 00:00:37,490 --> 00:00:38,590 cope with this demand. 9 00:00:38,720 --> 00:00:44,870 Advanced figures have introduced DSP blocks that are capable of performing high performance arithmetic 10 00:00:44,870 --> 00:00:45,630 operations. 11 00:00:45,680 --> 00:00:51,320 Therefore, nowadays there are two different types of resources available on FPGA to implement arithmetic 12 00:00:51,320 --> 00:00:54,250 operations, lookup tables and Espy's. 13 00:00:56,250 --> 00:01:02,780 In previous lectures, we understood that if pigs used lookup tables to implement logic circuits, including 14 00:01:02,800 --> 00:01:09,270 logical and arithmetic operations, después are reconfigurable computational blocks added to the FPGA 15 00:01:09,270 --> 00:01:14,670 architecture by winders to increase the design performance comparable to the Aztec counterpart. 16 00:01:15,190 --> 00:01:21,270 A typical DP block receives a couple of inputs and then passes them through a set of predesigned, reconfigurable 17 00:01:21,270 --> 00:01:23,580 addition and multiplication modules. 18 00:01:24,240 --> 00:01:31,740 This figure shows a simplified design of DSB 48 hour level in the Arctic seven FPGA using bases. 19 00:01:31,740 --> 00:01:38,430 Traymore almost all the data paths and computational modules inside the DSP are reconfigurable. 20 00:01:39,420 --> 00:01:45,120 As a necklace designer, we don't need to know the details of the DSP blocks and how to reconfigure 21 00:01:45,120 --> 00:01:49,570 them, they actually still manages all the configuration tasks for us automatically. 22 00:01:49,630 --> 00:01:56,130 However, being familiar with its structure and role in implementing arithmetic expressions helps us 23 00:01:56,220 --> 00:02:01,170 to guide the actual synthesis process to generate high performance art descriptions. 24 00:02:02,340 --> 00:02:09,690 At the heart of a DSB, there is a multiplier that accepts a 25 bit and then 18 bits to complement inputs 25 00:02:09,870 --> 00:02:13,370 and generates a 40 Tribbett to complement or result. 26 00:02:13,890 --> 00:02:20,740 This multiplier receives one of its inputs via a PRISM module and gives its output to a post other module. 27 00:02:22,050 --> 00:02:28,680 There are also other parts in ADP to provide enough data to implement different mathematical and logical 28 00:02:28,680 --> 00:02:33,840 expression, most data points inside the DSP can be registered in flipflops. 29 00:02:34,740 --> 00:02:41,190 In addition, the multiplier and additions inside the DSP can be implemented by a single stage combination 30 00:02:41,190 --> 00:02:44,660 or circuit or a multi-stage pipeline such. 31 00:02:46,060 --> 00:02:53,590 Let's see how a DSB can be reconfigured to perform a multiply by this attack directed acyclic graph 32 00:02:53,590 --> 00:02:59,800 represents this expression Let's assume ADP, the being put feeds the multiplier directly. 33 00:03:00,660 --> 00:03:04,330 And the input bypasses the other and is connected to the multiplier. 34 00:03:05,280 --> 00:03:10,890 Finally, the multiplier as a result gets to the output by avoiding all the operators along the path. 35 00:03:12,820 --> 00:03:15,880 It is we can also directly implement this expression. 36 00:03:16,830 --> 00:03:22,920 The corresponding deck shows two levels of operations, the first level is addition, and the second 37 00:03:22,920 --> 00:03:24,180 one is multiplication. 38 00:03:24,330 --> 00:03:30,150 And this diagram shows the related data path in a DSP block performing the arithmetic expression. 39 00:03:31,880 --> 00:03:38,330 In summary, both lookup tables and DSP blocks can be used to implement a combination of all pipeline 40 00:03:38,390 --> 00:03:40,610 implementation of an arithmetic expression. 41 00:03:42,270 --> 00:03:47,730 But the question is, how can we guide us into this process to choose between lookup tables and the 42 00:03:47,730 --> 00:03:50,670 Espy's, the next lecture cope with this question. 43 00:03:52,210 --> 00:03:58,780 These are our takeaway messages, these blogs provide an easy class computational performance for FPGA 44 00:03:58,780 --> 00:03:59,350 designs. 45 00:04:00,450 --> 00:04:06,750 An arithmetic expression can be implemented with lookup tables or the Espy's or a combination of both 46 00:04:06,750 --> 00:04:07,560 resources. 47 00:04:08,640 --> 00:04:15,240 Now the question, what is the data in the following, the speed that performs this arithmetic expression?