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The question of this lecture is, how can we describe an arithmetic expression in class to be synthesized

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into a combination?

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Alzaga I will focus on the clock time constraint to answer this question.

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There is a clock timing constraint attached to each design in place before explaining the role of this

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constraint in designing computational circuits, let's get familiar with the clock signal in general.

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More details about this signal and how to generate and use that in a design are explained in a separate

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course called digital system design.

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With high level sentences in FPGA sequential circuits, a clock signal has a square waveform, alternating

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between zero and one logic values.

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The clock period determines the duration of a cycle of the clock.

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In Nevada, this period is denoted by nanosecond.

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The clock signal can also be defined by its frequency, which is the number of cycles in a second.

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And it is the reciprocal of the clock you.

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And they regard HLS new project with a window called Solution Configuration shows a default clock period

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constraint assigned to the design and you can change that if it's required.

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The the off the clock period is nanosecond, for example, in this figure, the clock period isn't 10

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a.m. The clock period also can be determined by the clock frequency, but its unit is megahertz that

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should be mentioned explicitly.

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For example, in this case, the equivalent frequency is one hundred megahertz.

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The clock constraint also has another parameter called uncertainty, which is not our concern in this

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course as we are focusing on the combination of circuit design.

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The clock of a design can have a direct impact on the final hardware structure if the total design propagation

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delay is less than a clock period and the design doesn't use a memory so explicitly that HLS tool drops

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the clock signal during the sentences and generates a fully computational circuit.

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If the clock period is longer than the design propagation delay, the high level synthesis tool automatically

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escargots the operations over more clock cycles, and some operations might need to be implemented by

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using multi cycle resources.

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In this case, the operations are broken into several steps by adding flipflop memory cells between

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systems.

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Then the clock signal is used to save the results of each step and pass them to the next.

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The result of a circuit structure is called Pipeline, which is the subject of a separate course.

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As I mentioned in the previous slide announcement, the entire operation can be synthesized into a single

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cycle combination or circuit or a multi cycle sequential circuit using the pipeline structure.

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One of the key parameters to decide this election is the relation between the design propagation delay

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and the clock timing constraint assigned to the design.

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Let's use the evaluation aside to demonstrate this relation.

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Firstly, we need to create an Atlas project, choose a name for the project, for example, timing,

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underscore constrained vehicles, then choose the name of the design top function, such as timing,

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underscore constraint, then accept the ten nanosecond clock period as the design clock constraint.

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Don't forget to choose the basic storyboard as the underlying FPGA finally click on the finish button

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to generate the project.

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Now create a new design, fight a name it timing, underscore constraint that CPPIB then other design,

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top function, name timing, underscore constraint as this.

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The function receives two integer inputs and returns their multiplication.

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After synthesizing the design, the report shows the features of the generated combination of circuits,

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the propagation delay is about eight point forty seven nanosecond.

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The final circuit only utilizes lookup tables without any memory cells, which means it is a combination

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of a circuit.

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Also, harder ports only include function arguments.

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Let's have a look at the analysis perspective, the design timing shows only one control step, so it

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doesn't need any memory cell, such as flip flops to save data transferring between systems.

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Now, let's change the design period construct for this purpose, go to the synthesis perspective.

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And right, click on the solution one folder and select the solutions settings option now under the

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sentosa settings, change the clock period from ten to five, which means the design clock frequency

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would be two hundred megahertz.

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Then perform the synthesis again.

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If you have a look at the synthesis report, we will notice that the generator, the hardware is not

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conventional anymore as it utilizes 220 flipflops and there is a clock signal in the hardware portal.

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By looking at the analysis perspective, we can see that the design execution spans or five steps.

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Therefore, the design requires some memory cells, such as flipflops, to transfer data between steps.

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As can be seen, the synthesis process has utilized a pipeline multiplier to implement the multiplication

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operator in the code.

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The timing constraint is not the only parameter that impact on the result resource constraint is also

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another parameter that will be explained in the next election.

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These are our takeaway messages.

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There's a time constraint attached to each design in each of us choosing a proper clock period supports

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the Etchells to synthesize a description into a combination of Circa.

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Now, the quest for this election find a proper value for the clock period in which rather rituals to

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synthesize the following code into a combination of.