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After designing the purity of a generator, we should examine its behavior in action, so this lecture

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will synthesize the design for basis rebought.

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Firstly, download the zip file containing the design files located at the lecture resources and unzip

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that somewhere on your computer.

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In the welcome page, click on Create New Project Icon, then in the first page of the new project,

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bizarre insert parity underscored generator dash, futureless as the name and select the proper path

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for the project in the second Bizerte page and at the top function name and press on the ad finds bottom.

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Then go to the folder containing the design files and select the design header and source files.

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In the third resource page, press on the advise button and go to the folder where you save the design

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files and select to test bench header and source files in the fourth resource page.

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Don't forget to choose the basic three board as the target FPGA platform.

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In the generator project, you should see two design finds under the source folder and to test bench

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finds under the test bench folder.

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Open the design and test bench files and examine them as a design uses arbitrary production data types,

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the design header file includes the API underscore that each file, also a constant variable called

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W, is defined with the value of sixteen, which represents the width of the design input data.

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The design source file contains a top function and unrolled for loop describes its behavior.

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Notice that proper interfaces are defined in the top function, the test bench header file includes

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a design header fine and defines the design top function prototype that has been Sourcefire contains

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the main function, does not.

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This variable is defined in the main function to keep track of the test status.

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If all will be inside.

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The main function generates all the design input values, then it applies them to the design and compares

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the result with that of the software implementation.

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In the case of any discrepancy that satisfies people will be changed and proper messages printed on

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the screen.

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Now we can perform the simulation to check the design functionality.

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This is simulation report confirms the design functionality correctness.

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Now, let's perform the synthesis process.

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The report confirms that the results of the article hardbodies combination and it doesn't use any memory,

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so.

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In addition, the design ports correspond to the top function arguments directly.

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Here, I'm going to perform the RTL CECO simulation and check the design signals for this purpose in

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the simulation dialogue.

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Choose the all or ports option for the dumb race feature.

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After finishing the simulation, you can see the success of the design test, you can also see that

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the open wave, your icon is active now.

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Clicking on the icon opens the rebound away from viewer.

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In the waveform viewer unfold, the design top signals to see the waveforms on the right area.

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To zoom in on out the waveform, you can use the icons and the top ribbon toolbar or hold the control

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key and play with the mouse or scroll.

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Check a couple of inputs and outputs and make sure that the generated parity bits are correct.

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This lecture is the last in this section that explained the design concepts and techniques, so the

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next lecture will give you a couple of harder designs and exercises through which you review and master

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the proposed techniques in this section.

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This is our takeaway message, the design signals the way form can be dumped in a fine during Article

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six simulation to be checked later using the pivot away from pure.

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Now the question, what is the design propagation delay estimated by the Nevada test toolset?