The question motivated this election is how can we reduce the propagation delay of the party generator
digital circuit to improve its performance?
As we saw in the previous lecture, if you consider that the propagation delay of an or gate is Delta,
then the propagation delay of the whole design would be at least W minus one times Delta.
Traditionally, designers are responsible for dealing with all the details are providing an optimum
logic circuit.
However, nowadays, Etchells Tools can perform almost all details, just with a little help from designers
following a proper coding Stine's and Etchells optimization guidelines to be able to follow these coding
styles.
Understanding the underlying concept behind several optimization techniques is essential here.
I'm going to explain one of the computation related optimization idea using the power generator.
Addicts or operators are commutative and associative, restructuring the chain of gates into a balanced
three give the same result.
Therefore, this balance three also implements the parity with generate.
If you assume W equals to two to the power of N. despite oratory shows the power to generator, which
has any level of gates thrown W divided by two or gates in the first layer, w divided by four in the
second layer and one X or gate in the last layer, then it needs W minus one X or gaits in total.
If we consider the delta odelay for each X or gate, the delay of the circuit is a logarithmic function
of the bitrate, which is much less than that of our first implementation.
After understanding the concept of a part of it, the question is, how can we describe the power to
generate in each of us?
The next lecture will address this question.
The balance, three extra structure implements, apparently to generate.
That is optimized for performance.
Now, the question for the propagation delay of uneven parity with generator for an 11 data if the delay
of unexpurgated is one nanosecond.