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Let's design a digital circuit for the party we generate, let's consider to be data and its associated

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party.

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With this truth table shows the value of the event and operative its.

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That's can be seen, the parity is the inverse of the event.

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Also, an extra gate implements the even part of it.

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Therefore the following, the logical expression generates a parity bit for two bits, D1 and D2.

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INSEE, we can use bitwise Exaro operator to show this expression.

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Now, if you assume attribute data, then the circuit depicts the particle generator for the three bit

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data.

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Generalizing the idea of parity with generating using X or to convert a wide bit data is a straightforward

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each extra input adds an X or gate to the chain.

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Therefore, the parity bid for a binary value with W bits can be generated by a chain of at least minus

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one X or gaits.

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If there is one one zero zero one one zero zero, then the even part of it is zero.

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Let's have a look at the circuit propagation delay, if we consider that the propagation delay of an

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X or gate is Delta, then the propagation delay of the whole design is at least W minus one delta.

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Now, the question is, how can we reduce the circuit propagation delay to improve its performance,

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the next lecture will answer this question.

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This is our takeaway message, the chain of ex or gates can generate the parity bit for a binary data.

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Now, the quiz question, the following figure shows a four digit transmission line, the power to be

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the generator that source and transmit it along with the data at the destination there or detector circuit

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checks.

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Any single possible error along the line provide a logic circuit for the error detector.