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In this lecture, I am taking the parity-bit generator design as a typical example that contains a
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repetitive computing pattern which can be implemented by the parallel for-loop in HLS. 
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The parity-bit is a technique to detect a single-bit error in binary data.
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The binary data can become erroneous while it is saved in the memory or during the process of transmitting
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from one place to another. 
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Some bits may change their states because of different types of unpredicted events such as the interaction
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with energetic particles (or terrestrial radiations), magnetic fields or electric spikes. This phenomenon 
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is critical in nano-scale semiconductor technologies, nuclear power stations, satellites and aerospace 
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applications.
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Single Event Upset (also known as soft-error) is one of the famous models representing this type of error.
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This model assumes that one of the binary bits changes its state from 0 to 1 or from 1 to 0.
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As an example, a Single Event Upset in the flight computers of Airbus A330 on 7 
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October 2008 is suspected to result in an aircraft upset that nearly ended in its crashing after the 
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computers underwent several malfunctions.
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Parity is a simple mechanism to detect a single bit error in a binary data.
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The parity bit is a one-bit signature of an n-bit binary data that is usually saved or transmit with
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the data.
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A parity bit generator receives data and generates the parity-bit. Then this bit is attached to the data.
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Later, the parity-bit checker can check the validity of the parity-bit and detect any possible 
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single-error in the data. 
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There are two types of parity: odd parity and even parity.
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The idea behind this is that the total number of “1”s in a binary value should always be even or odd. 
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The parity bit should be generated to meet this constraint.
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The parity bit should be generated to meet this constraint.
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Let’s take a few examples:
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If we assume that the binary value is 0b1101001, then the number of 1s is 4, 
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which is even.
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In the case of even parity, the extra bit should be zero 
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that is p=0. 
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This makes the total number of 1’s in the (data+parity) value even. 
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In the case of odd parity, the extra bit should be 1 that is p=1. 
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This makes the total number of 1’s in the (data+parity) value odd.
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If the data is 1011101, which has five 1s, then even parity bit is 1 and 
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the odd parity-bit is 0.
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In the following lecture, I will explain how to implement the parity bit generator circuit using a set of 
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XOR gates.
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The takeaway messages are:  Parity-bit can be used to detect a single-bit error in a binary data
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There are two types of parity-bit: even and odd,  In the even parity, the (parity + data) should have an 
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even number of bits,  In the odd parity, the (parity + data) should have an odd number of bits
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Now the first quiz
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Find the even parity bit (pe) and odd parity bit (po) for the following data
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As the second quiz find the erroneous data in the following (parity+data) binary values.