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The loop unrolling technique cannot be applied to all loop statements in a code. A specific coding 
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style is required to be able to fully unroll a loop and synthesis it into a combinational circuit.
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In this lecture, I will explain some of the related coding styles.
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When we add the unroll pragma to a loop statement, the synthesis tool unrolls the code at compile time
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so it should know the exact number of loop iterations. 
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In other words, only loops with static bounds, which are fixed and know at compile time, can be 
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fully unrolled by the HLS tool. 
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The number of loop iterations can be defined through a macro such as this code in which N is defined 
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by a define macro.
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Alternatively, a const variable can be used, as shown in this code example.
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However, the for-loop in the third code cannot be unrolled as the number of loop iterations depends 
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on n which is a function input argument and is unknown at compile time. 
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Notice that in this case HLS tool gives a warning message and keeps the loop rolled and generates 
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a sequential circuit instead of a combinational one.
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Fully unrolling a loop structure results in a separate hardware circuit for each iteration. 
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Therefore, there should be enough hardware resources on the target FPGA to realise all the instances; 
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otherwise, the logic synthesis phase will issue an error.
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The Xilinx Vivado-HLS unrolls the loop and performs the high-level synthesis regardless of the 
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available hardware resources and only gives warning messages in its report. 
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However, if we don’t pay attention to the warnings, the Xilinx vivado logic synthesis tool later along
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the design flow will complain about the lack of enough resources and won’t generate the FPGA bitstream. 
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As an example, consider that our target FPGA has 20800 LUTs. 
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Let’s assume that one instance of the task function in this loop requires 100 LUTS.
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If N=10, after synthesising this code about 1000 LUTs are required. As it is less than 
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20800, the for-loop can be implemented later.
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However, if N=1000, then 100000 LUts are required. As it is greater than 20800, 
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20800, 
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it cannot fit in the target FPGA.
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In the next lecture, I will take a real example to explain how to use the unrolling techniques in practice. 
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The takeaway message from this lecture is: To fully unroll a loop in HLS,  The loop bounds must be known at 
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compile time.  And there should be enough resources on FPGA, e.g., enough LUTs
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Now the quiz question. Which code can be synthesised into a combinational circuit?