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Iteration statements or loops in a software language repeat a group of statements a certain number 
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of times, or while a condition is fulfilled. 
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These statements make the programming much more manageable and reduce the program code size. 
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Using iteration statements are also very useful in hardware design. 
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In this section, I will explain how to use parallel iteration statements in coding combinational hardware 
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designs.
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Iteration statemen	ts are part of the control flow in a software program. They help tasks execute several
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times, sequentially on a different data set. 
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These statements are introduced by the keywords 
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while, do, and for.
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Repetitive patterns can be seen in many hardware designs in which the same task should be applied to 
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a set of data, for example to all the bits in an n-bit data.
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However, there are differences between the execution of a software loop and a hardware loop. 
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The main difference is the parallelism execution in the combinational hardware circuits that is modelled 
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by dataflow, in contrast to the concept of sequential execution in software programs that is modelled 
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by control flow techniques.
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This section focuses on the techniques to use loop statements in describing combinational hardware circuits.
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This section consists of 10 lectures. This lecture introduces the section. The next lecture 
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gives you a big picture of a repetitive hardware structure to be used later throughout this section. Lecture
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three explains using a for-loop statement to describe a repetitive combinational pattern in HLS. The section 
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also introduces the loop unrolling optimisation technique.
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The loop unrolling technique cannot be applied to all loop statements in a code. Lecture four explains 
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a specific coding style for a loop to be synthesised into a combinational circuit.
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To demonstrate the combinational loop coding style, Lecture five will introduce the parity-bit generator 
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design example.
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Then Lecture six will explain its implementation in HLS.
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An optimisation technique to reduce the propagation delay of the parity generator digital circuit is 
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explained in the seventh lecture.
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Describing the optimised parity-bit generator in HLS would be the topic of the eighth lecture.  Lecture nine implements
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the optimised design in the Vivado-HLS.
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Finally, the last lecture will give you a couple of exercises to practise 
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all the concepts have been explained throughout this section.