To get ready to control the 7-segment displays on the Basys3 board using HLS, we should 1
know their configuration on this board. 2
So, let’s get ourselves familiar with this configuration. 3
According to this figure, there are four 7-segments available on this board that is connected to the FPGA 4
through 12 pins supporting control and data signals. Each 7-segment has a dedicated control pin 5
that determines its ON and OFF state. 6
Therefore, there are four control signals for 7-segments. To turn on a 7-segment, 7
the circuit driver in the FPGA should write a low voltage level or 0 value to the corresponding FPGA 8
pin. 9
There are eight data signals shared among four 7-segments. 10
Therefore, 7-segments activated at the same time, 11
show the same data. In order to show a four-digit number on the 7-segments, the time-multiplexing technique 12
should be applied to the data signals. 13
This multiplexing requires a sequential circuit design which is not the subject of this section. 14
I will describe complex sequential circuits to control 7-segments in the Sequential Circuits course, 15
which is the second course of this series on Digital System Design with High-Level Synthesis for FPGA. 16
As this section only focuses on combinational circuit design, we only control one 7-segment at 17
a time. 18
This figure shows the 7-segment connections along with their corresponding FPGA I/O pins. Four transistors 19
implement the control signal section. Therefore, to turn on the connected 7-segment to each 20
control signal, the logic value 0 should be applied to the corresponding FPGA I/O pin. 21
Also, the 8 data signals are shared among 7-segments. 22
The names of FPGA I/O pins are the key information that we will use later along this course. 23
After getting ourselves familiar with the 7-segments in Basys3 board, 24
the question is: How to control a 7-segment in HLS using a C-function? In the next lecture, 25
I will explain how to write a C code to control a single 7segment. 26
To control a seven-segment two groups of signals should be provided by a design in the FPGA: control and data signals. Data signals 27
are shared among multiple 7-segments. 28
We should know the names of the FPGA pins connected to the 7-segment display for constraint definition in our design. 29
Now, the quiz question. 30
Find control signal values and the data code to write the number 5 on the left-hand side 7-segment 31
and turn off the others.