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To get ready to control the 7-segment displays on the Basys3 board using HLS, we should 
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know their configuration on this board. 
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So, let’s get ourselves familiar with this configuration.
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According to this figure, there are four 7-segments available on this board that is connected to the FPGA 
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through 12 pins supporting control and data signals. Each 7-segment has a dedicated control pin 
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that determines its ON and OFF state.
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Therefore, there are four control signals for 7-segments. To turn on a 7-segment, 
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the circuit driver in the FPGA should write a low voltage level or 0 value to the corresponding FPGA 
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pin.
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There are eight data signals shared among four 7-segments. 
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Therefore, 7-segments activated at the same time,
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show the same data. In order to show a four-digit number on the 7-segments, the time-multiplexing technique
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should be applied to the data signals. 
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This multiplexing requires a sequential circuit design which is not the subject of this section. 
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I will describe complex sequential circuits to control 7-segments in the Sequential Circuits course, 
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which is the second course of this series on Digital System Design with High-Level Synthesis for FPGA.
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As this section only focuses on combinational circuit design, we only control one 7-segment at 
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a time.
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This figure shows the 7-segment connections along with their corresponding FPGA I/O pins. Four transistors 
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implement the control signal section. Therefore, to turn on the connected 7-segment to each
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control signal, the logic value 0 should be applied to the corresponding FPGA I/O pin. 
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Also, the 8 data signals are shared among 7-segments. 
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The names of FPGA I/O pins are the key information that we will use later along this course. 
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After getting ourselves familiar with the 7-segments in Basys3 board, 
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the question is: How to control a 7-segment in HLS using a C-function? In the next lecture, 
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I will explain how to write a C code to control a single 7segment.
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To control a seven-segment two groups of signals should be provided by a design in the FPGA: control and data signals. 	Data signals 
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are shared among multiple 7-segments.
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We should know the names of the FPGA pins connected to the 7-segment display for constraint definition in our design.
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Now, the quiz question.
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Find control signal values and the data code to write the number 5 on the left-hand side 7-segment 
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and turn off the others.