0
1
00:00:01,030 --> 00:00:06,430
In this lecture, we are going to synthesis the 7-segment controller code using the Xilinx Vivado-HLx 
1

2
00:00:06,850 --> 00:00:12,460
and generate the FPGA bitstream. The controller gets a single-digit decimal number and shows that on a 
2

3
00:00:12,460 --> 00:00:13,230
7-segment display. 
3

4
00:00:13,600 --> 00:00:16,030
We also check our design on the Basys3 board. 
4

5
00:00:17,690 --> 00:00:24,380
Firstly, run the Vivado-HLS IDE and create a new HLS project. Choose a project name, for example, 
5

6
00:00:24,560 --> 00:00:31,100
“single_digit_seven_segment-vhls” and select a proper 
6

7
00:00:31,100 --> 00:00:32,630
path for the project files.
7

8
00:00:33,500 --> 00:00:39,500
In the second step of the create new project wizard choose a design top-function name. Then
8

9
00:00:39,620 --> 00:00:42,950
choose the Basys3 board as the target FPGA platform.
9

10
00:00:45,660 --> 00:00:51,000
After creating the project, we should define the design files. For this purpose right-click on
10

11
00:00:51,000 --> 00:00:57,330
the source folder and create a New Files and name it “single_digit_seven_segment.cpp”.
11

12
00:00:57,330 --> 00:01:04,170
“single_digit_seven_segment.cpp”. Then, create the design header file with the name of “single_digit_seven_segment.h”
12

13
00:01:04,170 --> 00:01:11,040
“single_digit_seven_segment.h”. At this stage, we can create the source and header test bench files. 
13

14
00:01:11,040 --> 00:01:11,670
For this purpose,
14

15
00:01:11,800 --> 00:01:12,180
right-click on 
15

16
00:01:12,180 --> 00:01:16,050
the Test Bench folder and name the created files properly.
16

17
00:01:31,430 --> 00:01:37,340
As we are going to use arbitrary precision data types, open the design header file and include the 
17

18
00:01:37,340 --> 00:01:39,430
“ap_int.h” file.
18

19
00:01:40,100 --> 00:01:45,860
Now go to the design source file, include the header file and write the design top-function code.
19

20
00:01:47,070 --> 00:01:53,460
The top-function receives a single-digit decimal number through an 8-bit input argument called digit 
20

21
00:01:54,120 --> 00:01:58,020
and generates two groups of signals for the seven-segment. 
21

22
00:01:59,160 --> 00:02:05,220
The first group via the code7segment output argument defines the 7-segment data and the second 
22

23
00:02:05,220 --> 00:02:11,700
group through the anodes output argument enables the desired seven-segment. A switch-case 
23

24
00:02:11,700 --> 00:02:14,370
statement can implement the behaviour of the design. 
24

25
00:02:14,730 --> 00:02:20,430
The statement can select the proper 7-segment code corresponding to the value in the input argument.
25

26
00:02:28,690 --> 00:02:35,020
Also, we need a single assignment to enable the first 7-segment. For this purpose, the value of 
26

27
00:02:35,050 --> 00:02:39,410
1110 should be assigned to the anodes output argument.
27

28
00:02:40,060 --> 00:02:45,640
Finally, we should define the argument interfaces, but let’s deliberately leave them for later and 
28

29
00:02:45,640 --> 00:02:47,830
check what would happen in the synthesis report.
29

30
00:02:50,020 --> 00:02:55,630
Before synthesising the design code, we should make sure that its behaviour and functionality is correct. 
30

31
00:02:55,900 --> 00:02:56,770
For this purpose, 
31

32
00:02:56,950 --> 00:02:58,060
we need a test bench.
32

33
00:02:59,000 --> 00:03:05,480
If you haven’t created the testbench files yet, Create two files under the test bench folder under the 
33

34
00:03:05,480 --> 00:03:11,780
project in the Explorer view. The first file would contain the test bench source file, and another 
34

35
00:03:11,780 --> 00:03:13,160
is the test bench header file.
35

36
00:03:13,490 --> 00:03:18,680
The header file includes the design header file and defines the design top-function prototype.
36

37
00:03:19,630 --> 00:03:21,640
The source file should import the header file. 
37

38
00:03:23,470 --> 00:03:28,720
Let’s define an array that keeps all the 7-segment codes from 0 to 9.
38

39
00:03:30,410 --> 00:03:36,570
The source file contains the main() function. We need a variable that represents the status of the test 
39

40
00:03:36,570 --> 00:03:36,900
bench.
40

41
00:03:37,100 --> 00:03:40,150
Let’s call that status. At the end of the function, 
41

42
00:03:40,310 --> 00:03:44,560
we use the value of this variable to report the status of the design test.
42

43
00:03:45,830 --> 00:03:51,650
Then we need a for-loop to generate all the desired design input as the test vectors to be applied to 
43

44
00:03:51,650 --> 00:03:52,230
the design.
44

45
00:03:52,760 --> 00:03:55,940
Before that, we need to declare a couple of variables. 
45

46
00:03:57,590 --> 00:04:01,010
The for-loop generates all the numbers between 0 and 9. 
46

47
00:04:01,700 --> 00:04:07,270
Also, it applies them to the design and compares the result with the code in our array. 
47

48
00:04:09,050 --> 00:04:13,700
In the case of any discrepancy, it changes the status variable value.
48

49
00:04:18,650 --> 00:04:20,780
Now we are ready to perform the C-simulation.
49

50
00:04:33,390 --> 00:04:37,760
The C-simulation report confirms that the functionality of our design is correct. 
50

51
00:04:39,260 --> 00:04:42,230
Now let’s perform the HLS synthesis and check the report.
51

52
00:04:46,790 --> 00:04:50,060
As can be seen from the synthesis report, the design is combinational. 
52

53
00:04:50,570 --> 00:04:51,860
It doesn’t use any memory cell. 
53

54
00:04:51,860 --> 00:04:55,830
However, it has more ports that the top-function arguments.
54

55
00:04:56,120 --> 00:05:02,600
The reason is that we didn’t define the argument interfaces in the design top-function and HLS has 
55

56
00:05:02,600 --> 00:05:07,890
selected default interfaces for each port according to its type as an input or output. 
56

57
00:05:08,480 --> 00:05:12,370
So let’s go back to the design and add the required interfaces. 
57

58
00:05:12,740 --> 00:05:17,410
Now, after synthesis, we see only the function arguments in the port list.
58

59
00:05:32,420 --> 00:05:38,090
Let’s perform the RTL/C Co-simulation to make sure that the design after synthesis is correct.
59

60
00:05:45,130 --> 00:05:47,920
The report confirms the RTL design correctness.
60

61
00:06:00,000 --> 00:06:04,800
Now we are ready to generate the hardware-IP to be used later in a Vivado project.
61

62
00:06:17,290 --> 00:06:21,700
After greeting the design RTL-IP, we are ready for logic synthesis.
62

63
00:06:24,150 --> 00:06:31,350
So, Let’s create a new vivado project and name it “single_digit_seven_segment-vivado”
63

64
00:06:31,390 --> 00:06:35,880
Choose the Basys3 board as the target FPGA platform. 
64

65
00:06:48,740 --> 00:06:54,890
Create a block design by clicking on “Create Block Design” under IP Integrator in the Flow Navigator
65

66
00:06:54,890 --> 00:07:02,540
view. Then, accept the default name and press, OK. Add the generated IP to the Vivado repository, By pressing 
66

67
00:07:02,540 --> 00:07:08,750
the right-click somewhere in the Diagram window and select the “IP settings…” option. Then go to the Repository 
67

68
00:07:08,750 --> 00:07:13,700
under IP, and press on the plus icon. Select the Vivado-HLS project path. 
68

69
00:07:14,060 --> 00:07:18,590
The Vivado will search for any IP in the folder and add that to the repository.
69

70
00:07:25,660 --> 00:07:31,810
Add the IP to the design by clicking somewhere in the diagram window and selecting the “Add IP...” option. Make 
70

71
00:07:31,810 --> 00:07:33,140
the design ports external. 
71

72
00:07:33,520 --> 00:07:39,700
You can do this by holding the control key and selecting all ports and then right-click on one port
72

73
00:07:39,700 --> 00:07:41,830
and select the “Make external” option.
73

74
00:07:43,510 --> 00:07:46,990
Then you can rename ports to make them more descriptive. 
74

75
00:08:03,770 --> 00:08:10,250
Now we should connect the external ports to the FPGA pins by defining a few physical constraints.  For  
75

76
00:08:10,250 --> 00:08:15,590
this purpose, create a new constraint file. Then you can copy all the commented constraints provided 
76

77
00:08:15,590 --> 00:08:18,950
by the board vendor and uncomment the desired ones.
77

78
00:08:20,360 --> 00:08:26,840
We need eight switches to provide the input number for the design. Uncomment the required switch constraints 
78

79
00:08:27,260 --> 00:08:30,710
and replace the default port names with the design port names. 
79

80
00:09:09,870 --> 00:09:16,000
Notice that here I have made a mistake. Let’s keep the mistake to check the Vivado error message.
80

81
00:09:16,630 --> 00:09:22,380
Also, we need 7-segment constraints to connect the design output ports to the 7-segments on the 
81

82
00:09:22,380 --> 00:09:26,100
board. Uncomment them and change their names.
82

83
00:09:33,150 --> 00:09:39,080
To uncomment a couple of lines, you can select them and then press the ctrl and slash keys together.
83

84
00:10:35,390 --> 00:10:39,560
Now let’s Generate Output Products… and then Create HDL Wrapper…
84

85
00:11:09,500 --> 00:11:12,040
Now we are ready to generate the FPGA bitstream.
85

86
00:11:18,060 --> 00:11:22,500
However, there is an error in the design. Let’s examine the error message.
86

87
00:11:25,020 --> 00:11:30,540
There is a conflict VCC voltage between signals in digit port, for example, digit[7] and 
87

88
00:11:30,540 --> 00:11:30,900
digit[0]. 
88

89
00:11:31,680 --> 00:11:36,660
The error in voltage levels indicates that at least of the IOSTANDARD properties assigned to the 
89

90
00:11:36,660 --> 00:11:37,920
ports is not correct. 
90

91
00:11:38,490 --> 00:11:42,000
If we have a look at the constraint file, then we should correct the typo. 
91

92
00:11:43,150 --> 00:11:44,680
And generate the bitstream again.
92

93
00:12:09,720 --> 00:12:11,190
Now, we have another error message. 
93

94
00:12:11,850 --> 00:12:18,240
The error message indicates that at least one port has not been assigned to a location or I/O pin. This 
94

95
00:12:18,240 --> 00:12:23,610
message shows that at least one the ports does not have any assigned PACKAGE_PIN property.
95

96
00:12:24,150 --> 00:12:27,390
Let’s have a look at the constraint file again and find the problem.
96

97
00:12:43,200 --> 00:12:49,280
There is another typo at line 88. Lets correst that and generate the FPGA bitstream.
97

98
00:13:10,140 --> 00:13:13,610
Now we can program the FPGA and play with the design on the board.
98

99
00:13:37,860 --> 00:13:42,930
This lecture is the last in this section that explained the design concepts and techniques. So the 
99

100
00:13:42,930 --> 00:13:49,050
next lecture will give you a couple of hardware designs as exercises through which you review and master 
100

101
00:13:49,050 --> 00:13:50,870
the proposed techniques in this section. 
101

102
00:13:52,220 --> 00:13:57,560
This is our takeaway message.  If we don’t define the port interfaces in the HLS top-function, then 
102

103
00:13:57,560 --> 00:14:01,190
the synthesis tool will choose the default interface for each port 
103

104
00:14:01,340 --> 00:14:05,230
that depends on the corresponding argument definition and usage in the code. 
104

105
00:14:07,170 --> 00:14:13,470
Now the quiz question. Change the code such that the design can show a single-hex digit on 
105

106
00:14:13,470 --> 00:14:14,280
one 7-segment.