0
1
00:00:01,190 --> 00:00:07,220
7-segments are one of the basic display units on digital boards that can show decimal numbers. But 
1

2
00:00:07,220 --> 00:00:11,340
how can we control a 7-segment in HLS? In this section, 
2

3
00:00:11,480 --> 00:00:15,250
I am going to talk about 7-segments and how to use that in HLS.
3

4
00:00:16,880 --> 00:00:22,760
A 7-segment display is a handy and efficient mechanism to show a decimal number or some alphabetical
4

5
00:00:22,760 --> 00:00:28,760
information. 7-segments can be found on a wide range of digital circuits, such as digital
5

6
00:00:28,760 --> 00:00:31,160
clocks and digital control panels. 
6

7
00:00:33,400 --> 00:00:39,310
The Basys3 board contains four 7-segment displays connected to the FPGA. And, it is the designer 
7

8
00:00:39,310 --> 00:00:45,190
responsibility to design a logic circuit in the FPGA to control these 7-segments to show proper
8

9
00:00:45,190 --> 00:00:45,850
information.
9

10
00:00:48,150 --> 00:00:53,610
The 7-segment logic circuit driver should provide two groups of signals. The first group carries the
10

11
00:00:53,610 --> 00:00:59,640
data, which shows a number on a 7-segment, and the second group are control signals that select
11

12
00:00:59,640 --> 00:01:00,120
the target 
12

13
00:01:00,170 --> 00:01:05,640
7-segment. Multiple 7-segments share the same data signals and use them in a multiplex
13

14
00:01:05,640 --> 00:01:07,890
fashion managed by control signals. 
14

15
00:01:09,480 --> 00:01:14,650
To fully control a set of 7-segments display, a sequential circuit is required. 
15

16
00:01:14,700 --> 00:01:20,040
However, in this section that we are focusing on combinational circuits, I only explain the basic
16

17
00:01:20,040 --> 00:01:23,340
concepts and logic circuits to control one 7-segment display.
17

18
00:01:24,990 --> 00:01:30,300
I will describe more complex sequential circuits to control 7-segments in the Sequential Circuits 
18

19
00:01:30,300 --> 00:01:36,060
course, which is the second course of this series on Digital System Design with High-Level Synthesis
19

20
00:01:36,060 --> 00:01:36,780
in FPGA.
20

21
00:01:38,690 --> 00:01:41,120
This section consists of 11 lectures:
21

22
00:01:43,070 --> 00:01:45,600
The current lecture is an introduction to this section.
22

23
00:01:46,400 --> 00:01:50,720
The next lecture defines the structure of a seven-segment and its configurations.
23

24
00:01:51,830 --> 00:01:57,050
The 7-segment code associated with a numerical pattern will be explained in the third lecture.
24

25
00:01:57,920 --> 00:02:03,380
The fourth lecture discusses the 7segment displays configuration and their onboard connections 
25

26
00:02:03,380 --> 00:02:04,540
for the Basys3 board.
26

27
00:02:05,390 --> 00:02:11,390
The structure of the HLS code for showing a decimal digit on a single 7-segment is presented 
27

28
00:02:11,390 --> 00:02:12,170
in Lecture 5.
28

29
00:02:14,260 --> 00:02:20,610
To represent a multi-digit decimal number,  we need to use a proper coding mechanism. Binary Coded 
29

30
00:02:20,620 --> 00:02:27,550
Decimal (BCD) is the most common technique to show a decimal number in digital circuits. Lecture 6
30

31
00:02:27,700 --> 00:02:29,230
presents the BCD code .
31

32
00:02:31,180 --> 00:02:36,850
Later through lectures 7 and 8, I will explain two different techniques to convert a binary 
32

33
00:02:36,850 --> 00:02:38,710
number into its equivalent BCD. 
33

34
00:02:39,130 --> 00:02:44,440
After that, we go through an HLS code that displays a two-digit number on 7-segments. 
34

35
00:02:45,100 --> 00:02:48,490
For this purpose, the code activates a single 7-segment at a time.
35

36
00:02:49,750 --> 00:02:55,240
Lecture 10 is organised as a LAB through which I will clarify how to put all concepts and functions 
36

37
00:02:55,240 --> 00:02:58,330
together under the Xilinx vivado-HLx environment. 
37

38
00:02:58,750 --> 00:03:04,480
Finally, the last lecture contains a few exercises to review all the explained concepts in this section.
38

39
00:03:06,480 --> 00:03:09,660
What is the basic concept and structure behind a 7-segment?
39

40
00:03:10,350 --> 00:03:12,620
I will address this question in the following lecture.
40

41
00:03:14,400 --> 00:03:20,610
These are our takeaway messages: Using 7-segments is one of the common ways to display numerical 
41

42
00:03:20,610 --> 00:03:25,260
information on an electronic device. To drive a set of 7-segments
42

43
00:03:25,410 --> 00:03:30,780
two groups of signals are required, Data signals,  Control Signals
