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As the HLS design flow is a new topic, its learning requires a step-by-step approach with several examples. 
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The structure of this course is based on this assumption.
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This course is the first step towards using HLS to design logic circuits and computing algorithms 
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for FPGA-based platforms. 
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In this course, I will take the HLS approach to explain the fundamental concepts in digital design.
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I assume that you are not familiar with FPGA. However, it would be a bonus if you know FPGA 
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and the HDL design flow. 
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This course looks at FPGA from a high-level perspective without going into the low-level hardware details. 
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This course would give you the foundation of using HLS for digital design in Xilinx-based FPGAs to enhance 
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your productivity compared to the traditional HDL design flow. 
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You don’t need to have prior knowledge about FPGA. 
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Moreover, the course is designed such that you also don’t need to read other books or documents to 
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use 
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HLS
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However, referring to Xilinx documents, especially “Vivado Design Suite User Guide: High-Level 
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Synthesis-UG902” is recommended.
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For more examples and discussions about the HLS-based design approaches, you can refer to the 
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highlevel-synthesis.com web-log-site or the course Github site. 
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If you have any questions or issues regarding the concepts and codes presented in this course please 
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refer to the Q&A section.
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In this course, you’ll learn, What FPGA is,  How to use HLS design flow to implement different types 
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of combinational logic circuits, and how to work with state-of-the-art
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HLS software tools to implement algorithms on hardware.
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This is a practical course. Throughout the course, 
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I will explain the concepts of FPGA structure, software tools, HLS techniques, and coding styles 
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to implement several examples.
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This course comprises of four parts. 
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The first part is called prologue
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that introduces the course and its structure throughout two lectures. 
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The current video is the second lecture.
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The second part is called “introduction and setup” which gives a big picture of the FPGA technology and 
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its design flow and how to install related software tools and set up the target FPGA board. It consists 
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of two sections and 15 lectures, from lecture 3 to 17. 
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If you are already familiar with Xilinx FPGAs and the Xilinx Vivado and Vivado-HLS toolsets, then 
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you can skip this part. 
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The third part explains how to develop combinational circuits using C/C++ language in HLS. This part 
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consists of 9 sections and 88 lectures.
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Finally, the last part puts all explained techniques together to implement two exciting projects. 
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. It consists of two sections and six lectures.
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The first project implements a Home Alarm System. 
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It consists of two groups of sensors and detects any security breach in the system 
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and reports that properly. The second project implements a simple calculator which can perform 8
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operations and display the results on the seven-segments available of the Basys3 board.
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Each lecture describes a single idea which is presented through a couple of slides. 
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The first slide tells the topic and the motivation, then it follows by a few slides explaining the main ideas and concepts. 
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After that, a slide gives the motivation of the next lecture by posing a question. 
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This slide also creates a conceptual link between two consecutive lectures. 
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Then I summarise the lecture contributions through a few takeaway messages. 
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The last slide in each lecture contains a quiz that helps you to concentrate on the main idea.  
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In this course, I have considered the Xilinx Basys 3 FPGA board as our target platform. Basys 3 
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is an entry-level development platform based on the latest Artix-7 Xilinx FPGA designed exclusively 
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for Vivado Design Suite.
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However, the concepts and techniques explained along this course are valid for all other Xilinx FPGAs.
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What is the necessary information that we should know to start designing with HLS for FPGA? 
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This question will be answered in the following part, which consists of two sections. 
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The takeaway messages are, This course explains the fundamental of digital design using the Xilinx 
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HLS toolset
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You don’t need to have an in-depth hardware knowledge to follow this course
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Familiarity with C/C++ language is necessary
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As this lecture quiz, download the “Vivado Design Suite User Guide: High-Level Synthesis-UG902” 
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document and have a look at its Table of Contents.