0 1 00:00:00,690 --> 00:00:06,630 Hello and welcome to this course: Digital System Design with High-Level Synthesis for FPGA: Combinational 1 2 00:00:06,630 --> 00:00:07,170 Circuits 2 3 00:00:09,240 --> 00:00:15,510 Are you familiar with C/C++ language and would like to work with FPGAs straightaway without 3 4 00:00:15,510 --> 00:00:21,090 spending months and months learning complex hardware description languages? Then welcome to this course. 4 5 00:00:22,360 --> 00:00:29,320 Are you a software or hardware student who is going to learn the latest technologies about FPGA without spending 5 6 00:00:29,320 --> 00:00:34,480 too much to learn low-level tedious logic optimisation techniques? Then welcome to this course. 6 7 00:00:36,820 --> 00:00:42,700 Are you a researcher with software or hardware background who is going to take his or her research to 7 8 00:00:42,700 --> 00:00:47,800 the next level by accelerating algorithms with FPGAs? Then welcome to this course. 8 9 00:00:47,810 --> 00:00:49,650 I am Mohammad. 9 10 00:00:50,200 --> 00:00:53,150 I have a PhD in Electronics and Computer Engineering. 10 11 00:00:53,650 --> 00:00:58,360 I have been teaching electronics and programming courses in several universities for more than 10 years. 11 12 00:00:58,930 --> 00:01:04,350 I have been doing research on reconfigurable computing for more than 20 years in different universities. 12 13 00:01:04,960 --> 00:01:12,010 I am the author of several conference, journal and transaction papers, published by IEE/IEEE . 13 14 00:01:12,010 --> 00:01:12,400 and ACM 14 15 00:01:13,330 --> 00:01:18,590 Also, I have developed several real applications on FPGAs during my research career. 15 16 00:01:18,850 --> 00:01:21,150 I’ll be your instructor and guide in this course. 16 17 00:01:21,580 --> 00:01:27,430 My first goal is to simplify the new technologies in reconfigurable computing to be used by students 17 18 00:01:27,550 --> 00:01:31,450 and researchers who have no or little background knowledge of FPGA. 18 19 00:01:32,630 --> 00:01:35,160 You may have heard that FPGA design is complicated, 19 20 00:01:35,180 --> 00:01:41,570 yes, it is, if you follow the traditional HDL design flow. However, high-level synthesis design flow 20 21 00:01:41,690 --> 00:01:48,380 makes the FPGA design easy and accessible for a large group of software and hardware engineers. It 21 22 00:01:48,380 --> 00:01:53,720 is my mission here to uncover the high-level synthesis design secrets with a straightforward and exciting 22 23 00:01:53,720 --> 00:01:54,130 approach. 23 24 00:01:55,080 --> 00:02:00,810 We are going to learn, discover and explore the topic of high-level synthesis, HLS. 24 25 00:02:02,470 --> 00:02:05,810 HLS is an entirely new hardware design technology. 25 26 00:02:06,400 --> 00:02:12,970 It is a set of hardware design-flow, optimisation techniques, coding styles, software tools, and debugging 26 27 00:02:12,970 --> 00:02:13,690 mechanisms. 27 28 00:02:14,650 --> 00:02:21,460 HLS is a technology that uses a high-level language such as C/C++ to hide all the traditional hardware 28 29 00:02:21,460 --> 00:02:23,950 design complexities from designers. 29 30 00:02:25,190 --> 00:02:29,810 So, if you are curious about high-level synthesis and don’t know where to start, 30 31 00:02:29,990 --> 00:02:31,140 Welcome to this course. 31 32 00:02:32,370 --> 00:02:38,670 If you are a university or college instructor, lecturer, or professor who wants to add an HLS flavour 32 33 00:02:38,820 --> 00:02:43,440 to the traditional HDL hardware design flow, then welcome to this course. 33 34 00:02:44,690 --> 00:02:50,660 If you want to show that you are clever enough to work with FPGA like a pro just in a couple of days, 34 35 00:02:51,020 --> 00:02:52,310 then welcome to this course. 35 36 00:02:53,210 --> 00:02:56,270 This course is based on the Xilinx HLS technology, 36 37 00:02:57,160 --> 00:03:01,210 including software toolsets and FPGA-based hardware platforms. 37 38 00:03:02,080 --> 00:03:08,710 The technology is well presented, and there are several examples, designs, applications, and supports around 38 39 00:03:08,710 --> 00:03:08,910 it. 39 40 00:03:09,880 --> 00:03:14,830 presented in this course and provided by Xilinx or the HLS community. 40 41 00:03:16,270 --> 00:03:23,380 The technology is already used by several companies to design many commercial devices, including NVIDIA 41 42 00:03:23,380 --> 00:03:30,670 was able to simplify their code by 5X using HLS  HLS decreased design time by 50 per cent 42 43 00:03:31,090 --> 00:03:35,050 and overall development time, including verification, by 40 per cent. 43 44 00:03:36,230 --> 00:03:42,980 Google Develops WebM Video Decompression Hardware IP Using Technology Independent Sources and High 44 45 00:03:42,980 --> 00:03:43,760 -Level Synthesis 45 46 00:03:44,660 --> 00:03:48,740 This is a list of other companies that are using HLS in the design flows. 46 47 00:03:49,890 --> 00:03:55,710 In this course, I will use the Basys3 entry-level FPGA board to demonstrate several HLS design 47 48 00:03:55,710 --> 00:03:56,220 techniques. 48 49 00:03:57,330 --> 00:04:03,900 The Xilinx Vivado-HLx software toolset is used to develop logic designs starting from C/C++ code 49 50 00:04:04,140 --> 00:04:05,080 down to the FPGA 50 51 00:04:05,130 --> 00:04:05,390 bitstream 51 52 00:04:06,570 --> 00:04:12,770 If you have a budget of a few hundred pounds and are going to learn very advanced topics on HLS and FPGA, 52 53 00:04:12,990 --> 00:04:14,210 then welcome to this course. 53 54 00:04:15,700 --> 00:04:21,640 You only need to spend a couple of hundred pounds to purchase the Xilinx Basys 3 FPGA board, and 54 55 00:04:21,640 --> 00:04:25,600 all the software tools are available for free via the Xilinx website. 55 56 00:04:26,380 --> 00:04:32,170 This course is the first of its kind that builds the HLS design flow and skills along with the digital logic 56 57 00:04:32,170 --> 00:04:34,570 hardware circuit concepts from scratch. 57 58 00:04:35,880 --> 00:04:41,550 This course is the first of a series on HLS in designing hardware modules and accelerating algorithms 58 59 00:04:41,730 --> 00:04:47,640 on a target FPGA. Whereas this course focuses on combinational circuits, the other courses in the 59 60 00:04:47,640 --> 00:04:54,180 series will explain how to use HLS in designing sequential logic circuits, algorithm acceleration, 60 61 00:04:54,360 --> 00:04:57,780 and hybrid CPU plus FPGA heterogeneous systems.