1 00:00:01,330 --> 00:00:05,430 Holidays welcome to a physical design with MATLAB and smiling. 2 00:00:05,500 --> 00:00:07,100 We are from dystonia apart. 3 00:00:07,820 --> 00:00:10,420 So let's go to our jurisdiction. 4 00:00:10,450 --> 00:00:15,430 Actually we are in section 3 which is basic project with systems and generator and IPG. 5 00:00:16,060 --> 00:00:25,450 So we have three other electrician in this section three which are better than to design a basic hefty 6 00:00:26,930 --> 00:00:29,050 implementation on system generator. 7 00:00:29,060 --> 00:00:40,960 And we're going to pretty STEP ON OPERATION FOR OUR Spartan 3 and junk FPGA boards. 8 00:00:41,130 --> 00:00:49,040 So previously in Section 1 and 2 we all talk about installation and introduction so it's not about systems 9 00:00:49,060 --> 00:00:52,910 and later and your quarter is will it age old verified. 10 00:00:53,100 --> 00:00:58,350 So let's go in to Section 3 and we are two lapses here. 11 00:00:58,470 --> 00:01:04,660 So one is basic systems and a true design with a property and that is including the deck configuration 12 00:01:04,670 --> 00:01:12,710 part receiver systems and router so let's talk about basic system Senator designed for the actually 13 00:01:12,890 --> 00:01:14,950 affected parts for your transplant. 14 00:01:15,260 --> 00:01:31,180 So I have to do the processing of audio and some type of signal so it gendered the time no one signal 15 00:01:31,190 --> 00:01:33,130 into pregnant women signal. 16 00:01:33,430 --> 00:01:39,610 So I have to is have utilized for signal processing this project and system generator so we can see 17 00:01:39,610 --> 00:01:48,430 heard the design so determined to call a hefty block available it systems and later that is the interface 18 00:01:48,430 --> 00:01:56,230 between mad upstream link and I assume you are and we can see all the different components which are 19 00:01:56,230 --> 00:02:04,000 initialized in this design for implementing some audio processing type of project so here we are giving 20 00:02:04,000 --> 00:02:15,740 some sine wave for processing so that sine wave is generated in the wave from output medium of T so 21 00:02:15,740 --> 00:02:21,200 we can see here we have different type of symbolic blocks so some are sine wave generator. 22 00:02:21,560 --> 00:02:30,350 You can see the buffer and some subsystems so a sine wave can be generated from that DSP sine wave. 23 00:02:30,980 --> 00:02:35,400 And there are other building blocks also which are nice for getting that type of plug. 24 00:02:35,780 --> 00:02:42,850 And here is a good way in a block to Goodwin blockage here to provide input from the C William block 25 00:02:42,890 --> 00:02:43,910 to the FPGA. 26 00:02:44,720 --> 00:02:53,420 Sometimes we can utilize some symbolic blocks or to simply block provide some inputs to Fiji block. 27 00:02:53,490 --> 00:03:02,210 Then we need to have it we get way out the type of Fort block which actually takes RPG output and genders. 28 00:03:02,470 --> 00:03:04,670 Same warning environment assembly code. 29 00:03:05,370 --> 00:03:14,550 So we have utilized DP positive and seven point one core in the design so that f f g which we have utilized 30 00:03:14,550 --> 00:03:22,860 in the previous design is available it systems and narrator so these type of these are similar processing 31 00:03:22,870 --> 00:03:33,400 Block Well we systems that made it so this block can use either block ram or distributed RAM which uses 32 00:03:33,400 --> 00:03:34,310 an RPG. 33 00:03:34,320 --> 00:03:37,720 Why do we need to implement our design on that vision. 34 00:03:37,740 --> 00:03:44,510 This block can work and support right extra analytics for freedom so radical to Alex for. 35 00:03:45,170 --> 00:03:46,000 I have the algorithm 36 00:03:48,620 --> 00:03:56,970 and disable to block are heavily utilized for communication purposes so we can process frequency domain 37 00:03:56,970 --> 00:04:03,800 signal in communication and we can utilize a more listeners scheme for that type of signal so we can 38 00:04:03,800 --> 00:04:11,110 see different property for a hefty block customization so we can select the transform lanes we can select 39 00:04:11,110 --> 00:04:17,560 the implementation of some and targeted block frequency as well as we can see the outer bands of snow. 40 00:04:17,590 --> 00:04:25,090 So we have some fear factor scaring off some surrounding mode and actually we are going to talk about 41 00:04:25,090 --> 00:04:31,280 these variables in dilapidation and latches and will taken on by our other instructor. 42 00:04:31,670 --> 00:04:40,910 So we will have lab session in next period for this implementation on systems and later and we can see 43 00:04:40,920 --> 00:04:43,060 further sitting year that is implementation sitting. 44 00:04:43,070 --> 00:04:45,780 So we have no mistakes. 45 00:04:45,980 --> 00:04:53,630 Instead of using block RAM and memory up since that is what I will block them in distributed DRAM are 46 00:04:53,630 --> 00:04:57,330 we targeting the configuration settings. 47 00:04:57,470 --> 00:05:03,680 So we are going to have the largest for the implementation on systems entering next video and we have 48 00:05:03,680 --> 00:05:07,670 lap to do that is like T2 Lexus chicken. 49 00:05:07,670 --> 00:05:12,830 So it is creating that configuration for FPGA bought in system the narrator we also have lapses in the 50 00:05:12,830 --> 00:05:13,430 next video. 51 00:05:13,430 --> 00:05:13,960 How you work. 52 00:05:14,310 --> 00:05:16,860 Yes go through the sum total aspect of this. 53 00:05:17,030 --> 00:05:17,620 Absolutely. 54 00:05:17,660 --> 00:05:27,300 Check the interface for programming and develop FPGA from FPGA design tools like AC be bottler systems 55 00:05:27,300 --> 00:05:34,770 and data so we can create a jet configuration or we should create a conflagration programming RPG and 56 00:05:34,770 --> 00:05:39,510 training course simulation in the system know that an FPGA environment. 57 00:05:39,510 --> 00:05:43,810 So if we want to run the course simulation then we need to have it happen. 58 00:05:43,810 --> 00:05:44,120 Forget it. 59 00:05:44,130 --> 00:05:49,850 We need to clear the data configuration actually this how do we create it. 60 00:05:50,360 --> 00:05:52,190 Once it created it cannot be used. 61 00:05:52,220 --> 00:05:57,470 So this is like is the library so we can utilize it for further purposes also. 62 00:05:57,620 --> 00:05:58,580 So we can see. 63 00:05:58,880 --> 00:06:05,280 So we have the we have the design of fast create transform which we have listened to talk and that pathway 64 00:06:05,290 --> 00:06:12,870 or transformation takes some DSP sine wave and it actually utilise some buffer and that similar inputs 65 00:06:12,870 --> 00:06:15,250 that provide to FPGA block from Gateway. 66 00:06:15,890 --> 00:06:21,360 And finally the results are sewn into what complement and what do you do in school on some boy. 67 00:06:21,750 --> 00:06:22,720 So my scope there. 68 00:06:22,730 --> 00:06:33,600 So these designs are these designs these designs need some up configuration so why we need to implement 69 00:06:33,600 --> 00:06:41,430 this design on FPGA we need to have some git set up so that setup has recruited by that posse block. 70 00:06:41,490 --> 00:06:48,120 So this is actually customizing generator and after we generate everything so we can run the options 71 00:06:48,120 --> 00:06:53,190 of course in relation to discrimination of any other of some like and dissemination from this system 72 00:06:53,190 --> 00:06:57,990 blender dragon which we are Lapis on and we also have some wavy Scorpio. 73 00:06:58,050 --> 00:07:04,590 So actually these waves could be used for switching the output diesel so a decided combat connection 74 00:07:04,620 --> 00:07:11,430 between the two traditional design block and the dead simulator. 75 00:07:11,640 --> 00:07:20,890 So it actually provides inputs corresponding inputs up that fast but and transformed to our hardware 76 00:07:20,950 --> 00:07:25,670 tonnage will again give that that these years into the war scope. 77 00:07:25,810 --> 00:07:33,160 So how did your simulation is illustrative also how we can do the hurricane simulation and what the 78 00:07:33,160 --> 00:07:35,630 meaning of adequacy mission actually began. 79 00:07:35,750 --> 00:07:40,270 We can draw on our project from the system than it did to the hybrid and we can get I didn't get the 80 00:07:40,270 --> 00:07:47,020 region through the system generator so the process called hurricane simulation and indeed utilized for 81 00:07:47,020 --> 00:07:49,750 a better education but what is on how to design. 82 00:07:49,750 --> 00:07:56,620 So we get we should select some specific boards strategic blocks and interest reports which were we 83 00:07:56,620 --> 00:08:04,080 are going to exit from his detonator so that IP actually these IP actually need to have everything defined 84 00:08:04,090 --> 00:08:04,960 inside. 85 00:08:05,320 --> 00:08:06,920 So which port how. 86 00:08:07,000 --> 00:08:14,120 What are the plugs in which board we we are going to access on so that we can see the detection of of 87 00:08:14,160 --> 00:08:15,100 sincere. 88 00:08:15,130 --> 00:08:19,070 So we have to select the board we can get it on board. 89 00:08:19,090 --> 00:08:24,970 So we are going to get on board in the upcoming lab session and where we can select the synthesize tool. 90 00:08:25,290 --> 00:08:28,200 How ready scripts a language a tree. 91 00:08:28,330 --> 00:08:29,500 And we can go to 92 00:08:32,250 --> 00:08:34,620 set up some other properties also. 93 00:08:34,820 --> 00:08:40,820 So we need to set up the frequency you need to set the frequency board and some packaging of some like 94 00:08:40,820 --> 00:08:47,680 this is the main item so we can see we are creating new new board for Is it a simulation so that it 95 00:08:48,270 --> 00:08:54,530 named is apparently frequency is preventing us and being look at any scene and actually digit PIN location 96 00:08:55,340 --> 00:09:00,430 provided in the data is apparently used to Hardy. 97 00:09:00,440 --> 00:09:05,470 So we have your boundary scan of what is shown so we as have I had learned. 98 00:09:05,480 --> 00:09:09,030 Actually these are also variables which are provided by that user right. 99 00:09:09,230 --> 00:09:15,860 And we can see these data to type a table device so this is actually three as 590 is predicted is minus 100 00:09:15,860 --> 00:09:27,250 four and it is actually could only we combat the customizing form we can install it and we can load 101 00:09:27,250 --> 00:09:27,400 it. 102 00:09:27,400 --> 00:09:29,980 So let's call it the node and we will have to. 103 00:09:29,980 --> 00:09:37,820 Lapses in policy to design basic design in the system the later and second is creating the configuration 104 00:09:37,910 --> 00:09:38,300 system. 105 00:09:38,300 --> 00:09:40,240 SENATOR So thanks for watching. 106 00:09:40,250 --> 00:09:44,180 We will have lapses in an upcoming video from how the restructure.